• 한국전산유체공학회:학술대회논문집
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• 2008.08a
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• pp.60.4-60.4
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• 2008

• Geotechnical Engineering
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• v.22 no.7
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• pp.6-16
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• 2006

• Journal of the Korean institute of surface engineering
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• v.41 no.1
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• pp.12-15
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• 2008

The zinc oxide(ZnO) nanowires were deposited on Si(001) substrates by thermal chemical vapour deposition without any catalysts. SEM data suggested that the grown nanostructures were the well-aligned ZnO single crystals with preferential orientation. Back-gate ZnO nanowire field effect transistors(FET) were successfully fabricated using a photolithography process. The fabricated nanowire FET exhibits good contact between the ZnO nonowire and Au metal electrodes. Based on I-V characteristics it was found out that the ZnO nanowire revealed a characteristic of n-type field effect transistor. The drain current increases with increasing drain voltage, and the slopes of the $I_{ds}-V_{ds}$ curves are dependent on the gate voltage.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.553-554
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• 2006

In this paper, 77 GHz CPW power amplifier MMIC, which are consisted of a 2 stage driver stage and a power stage employing $8{\times}50um$ gate width, have been successfully developed by using 120nm $In_{0.4}AlAs/In_{0.35}GaAs$ Metamorphic high electron mobility transistors (MHEMTs). The devices show an extrinsic transconductance $g_m$ of 660 mS/mm, a maximum drain current of 700 mA/mm, and a gate drain breakdown voltage of -8.5 V. A cut-off frequency ($f_T$) of 172 GHz and a maximum oscillation frequency ($f_{max}$) of over 300 GHz are achieved. The fabricated PA exhibited high power gain of 20dB only with 3 stages. The output power is measured to be 12.5 dBm.

• Proceedings of the Korean Geotechical Society Conference
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• 1991.10a
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• pp.362-375
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• 1991

Background and Necessity of the study : For more than 20 years, the soil engineering reserach group of Chonnam National University has been performing the deformation analysis of soft clayey foundation, since the University is located near the south-western coast of Korean Peninsulla, along which tide reclamation works have been under proaressing. Associsted with the fact mentioned above, the researchers have been developing a computer program in order to carry out deformation analysis of soft foundation since early 1980. Case-studies : In this research, the Biot's equation was selected as the governing equation coupled with several constitutive models including original and modified Cam-clay models, elasto-viscoplastic model, Lade's model etc. The anisotropy of soi1 can be considered in this program. To validate the accuracy of the computer program developed a couple of case-studies were performed. These include the pilot banking, sand drain considering smear effect and compound foundation reinforced with sheet pile into soft foundation.i) The pilot banking Good results could be acquired by assuming banking load as the body force composed of finite element mesh rather than equivalent concentrated load.ii) The sand drain Due to smear, the delay of consolidation was remarkable at the early stsge. so safety for the failure of foundation should be checked for the initial step of consolidation. iii) The compound foundation Accurate results were obtained by introducing the joint element method for the soft foundation reinforced with sheet pile into soiㅣ.

• Journal of Electrical Engineering and information Science
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• v.3 no.2
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• pp.261-266
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• 1998

This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

• Journal of the Semiconductor & Display Technology
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• v.12 no.4
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• pp.21-25
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• 2013

This paper is for enhancing the breakdown voltage of MHEMTs with an InP-etchstop layer. The fully removed recess structure in the drain side of MHEMT shows that the breakdown voltage enhances from 2 V to 4 V in the previous work. This is because the surface effect at the drain side decreases the channel current and the impact ionization in the channel at high drain voltage. In order to increase the breakdown voltage at the same asymmetric gate-recess structure, the InGaAs channel structure is replaced with the InGaAs/InP composite channel in the simulation. The simulation results with InGaAs/InP channel show that the breakdown voltage increases to 6V in the MHEMT as the current decreases. In this paper, the simulation results for the InGaAs/InP channel are shown and analyzed for the InGaAs/InP composite channel in the MHEMT.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.317-320
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• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Journal of Satellite, Information and Communications
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• v.8 no.1
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• pp.45-53
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• 2013

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latch-up problem during normal operation. However, a modified NEDSCR device with proper junction/channel engineering using counter pocket source (CPS) ion implantation demonstrates itself with both the excellent ESD protection performance and the high latch-up immunity. Since the CPS implant technique does not change avalanche breakdown voltage, this methodology does not reduce available operation voltage and is applicable regardless of the operation voltage.

• Transactions of the Korean Society of Automotive Engineers
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• v.19 no.5
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• pp.51-57
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• 2011

Parametric studies based on analysis of lubrication system of a four cylinder gasoline engine are illustrated system in this paper. In development process of engine lubrication system, parts of failure cases are related with oil pull over and oil churning phenomenon. The crankcase & head system pressure by oil churning phenomenon are gradual increased. It cause oil pull over phenomenon at engine breather line and oil over-consumption. In order to improve oil reduction and oil pull over phenomenon are also considered in the developing state. For this study, the characteristics of engine lubrication system are measured at various tilting angle and drain hole sizes. In addition, the oil flow & oil quantity are tested by blow by meter and catch jar. Results are presented to stabilize the oil supply system at sever driving condition. The data from present study are available for the engine lubrication system.