• Journal of IKEEE
• /
• 제16권4호
• /
• pp.283-289
• /
• 2012

In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• 제11권3호
• /
• pp.570-576
• /
• 2007

In this study, the characteristics of metal-ferroelectric-semiconductor FET (MFSFET) device is investigated using field-dependent polarization and square-law FET models. From drain current with the gate voltage variation, when coercive voltages of ferroelectric thin film are 0.5 and 1V, the memory windows are 1 and 2V, respectively. When the gate voltages are 0, 0.1, 0.2 and 0.3V, the difference of saturation drain currents of the MFSFET device at two threshold voltages in ID-VD curve are 1.5, 2.7, 4.0, and 5.7mA, respectively. As a result of the analysis for drain currents after tine lapse, which is based on the simulation for hysteresis loop and the fitting of retention properties of ferroelectric thin films such as PLZT(10/30/70), PLT(10) and PZT(30/70) thin film shows excellent reliability that the decrease of saturation current is about 18% after 10 years.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• 제11권1호
• /
• pp.83-88
• /
• 2007

The reliability characteristics of class-E RF power amplifier are studied, based on the degradation of MOSFET electrical characteristics. The class-E power amplifier operates as a switch mode operation to achieve high efficiency. This operation leads to high voltage stress when MOSFET switch is turned-off. The increase in threshold voltage and decrease in nobility caused by high voltage stress leads to a drop in the drain current. In the class-E power amplifier the effects caused by the degradation of MOSFET drain current is a drop of the power efficiency and output power. But the small inductor in the class-E load network allows the reliability to be improved. After $10^{7}\;sec$. the drain current decreases 46.3% and the PAE(Power Added Efficiency) decreases from 58% to 36% when the load inductor is 1mH. But when the load inductor is 1nH the drain current decreases 8.89% and the PAE decreases from 59% to 55%.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• 제12권3호
• /
• pp.534-540
• /
• 2008

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results is analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse, are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of neural networks.

• Proceedings of the IEEK Conference
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.615-618
• /
• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• Proceedings of the Korean Geotechical Society Conference
• /
• 한국지반공학회 1993년도 토목섬유
• /
• pp.65-90
• /
• 1993

• Geotechnical Engineering
• /
• 제24권8호
• /
• pp.9-13
• /
• 2008

• Geotechnical Engineering
• /
• 제19권8호
• /
• pp.40-44
• /
• 2003

• Geotechnical Engineering
• /
• 제23권2호
• /
• pp.16-26
• /
• 2007

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• 제22권12호
• /
• pp.1060-1068
• /
• 2011

In this paper, Current-Mode Class-D(CMCD) RF Power Amplifier(PA) is designed and implemented at 900 MHz. Conventional CMCD PA has output parallel resonator to reconstruct a fundamental frequency component of the output signal. However the resonator can be removed by connecting inverse class-F PAs because even-harmonic components can be removed by CMCD PA's push-pull structure. Using load-pull, inverse class-F PA with GaN transistors is designed, and CMCD PA with the inverse class-F PA is implemented. The CMCD PA has 64.5 % drain efficiency, 34.2 dBm output power. Comparing with the drain efficiency of a CMCD PA with parallel resonator, the CMCD with the inverse class-F technology has 13.6 % improved drain efficiency.