• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.451-462
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• 1997

A 2-dimensional numerical analysis is presented for thermal-electron heat conduction effects upon the electron transport and the drain current-voltage characteristics of submicron GaAs MESFETs, based on the use of a nonstationary hydrodynamic transport model. It is shown that for submicron GaAs MESFETs, electron heat conduction effects are significant on their internal electronic properties and also drain current-voltage characteristics. Due to electron heat conduction effects, the electron energy is greatly one-djmensionalized over the entire device region. Also, the drain current decreases continuously with increasing thermal conductivity in the saturation region of large drain voltages above 1 V. However, the opposite trend is observed in the linear region of small drain voltages below 1 V. Accordingly, for a large thermal conductivity, negative differential resistance drain current characteristics are observed with a pronounced peak of current at the drain voltage of 1 V. On the contrary, for zero thermal conductivity, a Gunn oscillation characteristic is observed at drain voltages above 2 V under a zero gate bias condition.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.271-272
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• 2007

Displacement current $(I_{dis})$ and drain-to-source current $(I_{DS})$ are evaluated using the simultaneous measurements of source $(I_S)$ and drain $(I_D)$ currents during the application of a constant drain voltage and a triangular-wave gate voltage $(V_{GS})$ to top-contact pentacene thin-film transistors.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.779-782
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• 2003

The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence and the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60 nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 10$^{5}$ at low drain voltage regime in drain current to gate voltage characteristics.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.2
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• pp.111-116
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• 2001

Poly-Si TFT's(Polysilicon thin filmtransistors) have been actively studied due to their applications in active matrix liquid crystal displays and active pull-up devices of CMOS SRAM's. For such applications, the leakage current has to be in the range of sub-picoampere. However, poly-Si TFT's suffer from anomalous high leakage currents, which is attributed to the emission of the traps present at gain boundaries in the drain junction. The leakage current has been analyzed by the field emission via grain-boundary traps and thermionic field emission over potential barrier located at the grain boundary. We found that the models proposed before are not consistent with the experimental results at far as drain-offset poly-Si TFT's we fabricated concern. In this paper, leakage current of drain-offset poly-Si TFT's with different offset lengths was studied. A conduction model based on the thermionic emission of the tunneling electrons is developed to identify the leakage mechanism. It was found that the effective grain size of the drain-offset region is important factor in the leakage current. A good agreement between experimental and simulated results of the leakage current is obtained.

• Electrical & Electronic Materials
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• v.9 no.10
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• pp.1001-1007
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• 1996

The conduction mechanisms of the off-current in low temperature (.leq. >$600^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT'S) have been systematically studied. Especially, the temperature and bias dependence of the off-current between hydrogenated and nonhydrogenated poly-Si TFT's were investigated and compared. The off-current of nonhydrogenated poly-Si TF's is because of a resistive current at low gate and drain voltage, thermally activated current at high gate and low drain voltage, and Poole-Frenkel emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation it has shown that the off -current mechanism is caused mainly by thermal activation and that the field-induced current component is suppressed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Electrical & Electronic Materials
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• v.10 no.1
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.90-93
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• 1996

The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

• Electrical & Electronic Materials
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• v.9 no.6
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• pp.558-563
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• 1996

We fabricated high voltage hydrogenerated amorphous silicon thin film transistors (a Si:H HVTFT) and investigated its temperature dependent characteristics of from 303 K to 363 K. The results show that the drain current was decreased at low gate voltage and increased at high gate voltage exponentially. According to the increasing the thickness of a Si layer, drain current increased. Difference of drain current at 363 K was increasd at the lower gate voltage and decreased at the higher gate voltage. When the drain and gate voltage of 100 V applied, the drain current increased linearly with rise temperature.