• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.967_968
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• 2009

For lighting application, high-power LED nowadays is driven at 350mA and a sensing resistor is used to provide feedback for LED-current regulation. This method adds an IR drop at the output branch, and limits power efficiency as LED current is large and keeps increasing. In this paper, a power efficient LED-current sensing circuit is proposed. The circuit does not use any sensing resistor but extracts LED-current information from the output capacitor of the driver. Controlling the brightness of LEDs requires a driver that provides a constant, regulated current. In one case, the converter may need to step down the input voltage, and, in another, it may need to boost up the output voltage. These situations often arise in applications with wide-ranging ""dirty"" input power sources, such as automotive systems. And, the driver topology must be able to generate a large enough output voltage to forward bias the LEDs. So, to provide this requirements, 13W prototype Buck-Boost Converter is used.

• Journal of Advanced Marine Engineering and Technology
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• 제39권8호
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• pp.821-827
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• 2015

This study concentrates on a wave energy converter with floaters that extracts the ocean's energy by moving up and down with the wave motion. The floater is connected to an arm structure, including a hydraulic cylinder that drives a hydraulic generator. This study focuses on a structural analysis of the floater unit, including arm and cylinder components, platform and jack-up system, along with spud columns. Previous studies have been conducted for miniature models for experimentation, but this study focuses on the full-scale model structural analysis. Static structural analysis is conducted using fine numerical grids. Due to the complexity of the whole model, it is analyzed in separate pieces. The floater unit, with arm and cylinder, are combined into one system. The platform is analyzed separately as a single system. There are four jack-up systems for each spud column; only one jack-up system is analyzed, as uniform loads are assumed on each system. There are several load cases for each system, all of which are analyzed thoroughly for stress (von Mises, shear, and normal) and deformation. Acceptable results were obtained for most of the components; unsafe components were redesigned.

• 전기학회논문지
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• 제59권2호
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.

• 전력전자학회논문지
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• 제25권5호
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• pp.333-342
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• 2020

Power exchanges between the grid and the battery through a bidirectional DC-DC converter are essential for DC microgrid systems. In general, the battery is charged when the grid is connected, and the system is powered by the battery when the grid is disconnected. In this mode transition, the saturation of the voltage controller slows down output response and produces large transient errors in DC link voltage. To solve this problem, a novel anti-windup design is proposed to improve anti-windup performance further. The proposed method stabilizes DC bus voltage through a wider range of battery voltage with faster transition compared with that of conventional methods. The proposed method is verified through an experimental setup composed of a 125 W laboratory-scale DC microgrid system.

• Journal of Power Electronics
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• 제17권6호
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• pp.1422-1432
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• 2017

This paper presents a buck-boost converter-based bipolar pulse generator, which is able to generate bipolar exponential pulses across a resistive load. The concept of the proposed approach depends on operating the involved buck-boost converters in discontinuous current conduction mode with high-voltage gain and enhanced efficiency. A full design of the pulse generator and its passive components is presented to ensure generating the pulses with the desired specifications (rise time, pulse width, and pulse magnitude) for a given load resistance and input dc voltage. In case of moderate pulsed output voltages (i.e. few of kV), one module of the presented bipolar generator can be employed. While in case of high-voltage pulsed output, multi-module version can be employed, where each module is fed from an isolated dc source and their outputs are connected in series. Simulation models for the proposed approach are built to elucidate their performance in case of one-module as well as multi-module based generator. Finally, a scaled-down prototype for one-module of buck-boost converter-based bipolar pulse generator is implemented to validate the proposed concept.

• 전기학회논문지
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• 제57권6호
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• pp.951-958
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• 2008

This paper describes development of hardware simulator for the PMSG wind power system, which was designed considering wind characteristic, blade characteristic and blade inertia compensation. The simulator consists of three major parts, such as wind turbine model using induction motor, PMSG generator, converter-inverter set. and control system. The turbine simulator generates torque and speed signals for a specific wind turbine with respect to given wind speed. This torque and speed signals are scaled down to fit the input of 2kW PMSG. The PMSG-side converter operates to track the maximum power point, and the grid-side inverter controls the active and reactive power supplied to the grid. The operational feasibility was verified by computer simulations with PSCAD/EMTDC, and the implementation feasibility was confirmed through experimental works with a hardware set-up.

• Journal of Power Electronics
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• 제12권1호
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• pp.98-103
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• 2012

This paper presents a digital pulse width modulator (DPWM) with a reduced digital modulation delay (a transport delay of the modulator) during the transient response of power converters. During the transient response operation of a power converter, as a result of dynamic variations such as load step-up or step-down, the closed loop controller will continuously adjust the duty cycle in order to regulate the output voltage. The larger the modulation delays, the larger the undesired output voltage deviation from the reference point. The three conventional DPWM techniques exhibit significant leading-edge and/or trailing-edge modulation delays. The DPWM technique proposed in this paper, which results in modulation delay reductions, is discussed, experimentally tested and compared with conventional modulation techniques.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.69-72
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• 2000

This paper shows the more improved design of MRI receiver compared to conventional one based on Elscint Spectrometer. At first, the low-cost ADC is 16 bits, 3MHz sampling A/D converter Comparing to conventional one with signal bits of 14 bits, this device with those of 16 bits helps getting Improved the image resolution improved. If frequency is designed centering around 7.6 MHz to be satisfied in 10 MHz of maximum input bandwidth of ADC. For 1st demodulation, fixed IF is used for the purpose of the implementing multi nuclei system. Control parts & partial digital parts are integrated on one chip(FPGA). In DDC(Digital Down Converter), we got required bandwidth of LPF by controlling its decimation rate. With above considerations, we designed optimal receiver for high resolution imaging to be implemented through PC interface & experimental test of receiver of MRI after receiver's fabrication.

• 전자공학회논문지S
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• 제34S권5호
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• 한국군사과학기술학회지
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• 제10권4호
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• pp.132-137
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• 2007

The dynamic range of the radar which uses digital signal processors is limited by ADC(Analog-to-Digital Converter). That parameter and ADC loss depend on the noise level of radar receiver. In order to stabilize the performance of radar systems, it is necessary to maintain the noise level constantly. This paper presents the noise AGC(Automatic Gain Control) concept that can keep the noise level constantly and proves that the concept is acceptable through the hardware test and evaluation.