• Journal of Korean Society for Quality Management
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• v.32 no.4
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• pp.169-183
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• 2004

The synthetic control chart (SCC) proposed by Wu and Spedding (2000) is to detect shifts in the process mean. The performance was re-evaluated by Davis and Woodall (2002), and the steady-state average run length (ARL) performance was shown to be inferior to cumulative sum (CUSUM) or exponentially weighted moving average (EWMA) chart This paper proposes a simple adaptive scheme to improve the performance of the synthetic control chart. That is, once a non-conforming (NC) sample occurs, we investigate the next L-consecutive samples with larger sample sizes and shorter sampling intervals. We employ a Markov chain model to derive the ARL and the average time to s19na1 (ATS). We also propose a statistical design procedure for determining decision variables. Comprehensive comparative study shows that the proposed control chart is uniformly superior to the original SCC or double sampling (DS) Χ chart and comparable to the EWMA chart in ATS performance.

• The Korean Journal of Applied Statistics
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• v.21 no.4
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• pp.675-694
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• 2008

We propose a new sampling design for the Korean Livestock Production Cost Survey. In this sampling design, the survey population is derived from the 2005’s agricultural census of Korea. And coefficient of variation(CV) is estimated from the current livestock production cost survey data, and the estimated CV’s are used to find the optimal sample size which satisfies the predetermined precision of estimation. In order to save the enumeration cost, the agriculture enumeration districts are used as a primary sampling unit(psu). Final sample is selected by double sampling. Also, we propose the estimator which is able to reflect the change of the population of livestock production households.

• The Korean Journal of Applied Statistics
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• v.8 no.1
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• pp.27-38
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• 1995

In the surveys of sensitive issues of the population that is composed of several unknown-size stratum, we propose the unrelated question model with quantitative attribute by using stratified double sampling. And, we consider two types of sample allocations under the fixed cost, which are the proportional allocation, the optimum allocation. In efficiency, the proosed model is inferior to the unrelated question model with quantitative attribute by stratified sampling in case of the size of each stratum is known. But we find that efficiency of the proposed model is increased, when the selecting probability of sensitive question p is small and first stage sample size n' is large.

• Journal of Korean Institute of Industrial Engineers
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• v.23 no.2
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• pp.289-305
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• 1997

In this paper, design procedure and estimation of the double sampling plans are developed when the production process is examined in order and if it shows the dependence between the products. If a dependent process model can be simulated, the best sampling plans can be selected by using the special properties of the probability structure. The number of actual evaluations to find the plans can be reduced remarkably. The experimental study reveals that only small portion of the total exhaustive enumeration is needed. ARMA (1,1) time series models are given as numerical examples.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• The Korean Journal of Applied Statistics
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• v.22 no.6
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• pp.1289-1300
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• 2009

The double sampling scheme is effective in reducing the sampling cost. However, the doubly sampled data is contaminated by two types of error, namely false-positive and false-negative errors. These would make the statistical analysis more difficult, and it would require more sophisticate analysis tools. For instance, the Wald method for the interval estimation of a proportion would not work well. In fact, it is well known that the Wald confidence interval behaves very poorly in many sampling schemes. In this note, the property of the Wald interval is investigated in terms of the coverage probability and the expected width. An alternative confidence interval based on the Agresti-Coull's approach is recommended.

• Journal of the Korean Statistical Society
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• v.14 no.2
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• pp.100-117
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• 1985

This paper describes an outline of the sampling design for crop area survey and product survey in Korea. The design attempts to from a double statification, to obtain an efficient allocation of the sample and to reduce the sampling error by establishign crop concentrated strata. The optimum numbers of sample field and sample plot are investigated. The design is made it possible to reduce the sampling errors as well as to reduce the sample size further than the present survey.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1993.04a
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• pp.302-302
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• 1993

• Industrial Engineering and Management Systems
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• v.14 no.2
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• pp.183-195
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• 2015

In this paper, we propose a two-stage group acceptance sampling plan for generalized inverted exponential distribution under truncated life test. Median life is considered as a quality parameter. Design parameters are obtained to ensure that true median life is longer than a given specified life at certain level of consumer's risk and producer's risk. We also explore situations under which design parameters based on median lifetime can be used for other percentile points. Tables and specific examples are reported to explain the proposed plans. Finally a real data set is analyzed to implement the plans in practical situations and some suggestions are given.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.