• 전자공학회논문지
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• 제53권1호
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• pp.139-144
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• 2016

본 논문은 가변 스위칭 주파수 PFM을 이용한 DC-DC 변환기의 집적회로 개발 시, 적용 가능한 주요 기능 블록의 설계에 관한 것이다. DC전압 변환 시 부하에 공급되는 전류가 작거나 출력전압이 설정값 근처에 도달했을 때 PFM 모드로 동작시켜 전력변환 효율을 높일 수 있다. PFM DC-DC 변환기 구현에 필요한 PFM 신호 발생회로, PFM 주파수 제어기, 출력전압감지회로 그리고 과전류보호회로를 설계하였다. 설계를 위한 공정파라미터는 내압 12[V], 최소선폭 $0.35[{\mu}m]$, 2P_2M CMOS 공정을 사용하였다.

• 전력전자학회논문지
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• 제17권1호
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• pp.1-7
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• 2012

This paper describes the performance comparison results for current controller of a single-phase PFC converter with 1-switch voltage doubler strategy for single-phase double-conversion UPS(Uninterruptible Power Supply). A single-phase PFC converter with 1-switch voltage doubler strategy needs a diode bridge and one bidirectional active switch. Thus it is possible to reduce the material cost. However, the study results of current controller design and comparison of current control method has not been known after the converter circuit was proposed. For the performance comparison of current control, single-phase 3 kVA double-conversion UPS was tested. The performance of PI and PR current controller is experimentally confirmed with followings - input current reference tracking, input power factor correction and input current THD suppression.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.45-48
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• 2001

An programmable current-mode folding and interpolation analog to digital converter (ADC) with programmable interpolator is proposed in this paper. A programmable interpolator is employed not only to vary the resolution of data converter, but also to decrease a power dissipation within the ADC. Because of varying the number of interpolation circuits, resolution is vary from 6 to 10bit. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The experimental result shows the power dissipation from 26 to 87mW with a power supply of 3.3V.

• 전기학회논문지P
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• 제61권3호
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• pp.122-128
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• 2012

An interleaved boost converter has many advantages such as current ripple reduction, switching effective double, etc. Due to these advantages, the interleaved boost converter applies to the power factor correction circuit. However, there are almost no analysis results because the input voltage and current are time-varying system in the power factor correction application. Therefore, in this paper, the current ripples of the power factor correction circuit using single-phase boost dc-dc converter and 2-phase interleaved boost dc-dc converter are compared and analyzed in detail. In order to verify the validity, computer simulation and experimental are performed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.235-237
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• 2006

This paper proposes a DC-DC converter which is able to charge and discharge secondary batteries. The converter operates as a double-ended forward converter in charging process and as electrical isolated boost converter in discharging process. The converter is designed for continuous current operation. The switching frequency is selected as 100kHz to reduce the size of both the inductor and the capacitor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1052-1054
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• 2001

This paper describes a boost converter to be operated at the boundary of continuous current mode(CCM) and discontinuous current mode(DCM) for power factor correction and low cost. A control method to be utilized in simulation is a average-current mode method in case of operating in CCM. The simulation results show that Better is the CCM converter then the DCM converter in harmonic content and input current waveform. And A Double-boost converter is superior to single-boost converter for input-current harmonic.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 전문대학교육위원
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• pp.14-16
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• 2004

This paper describes a boost converter to be operated at the boundary of continuous current mode(CCM) and discontinuous current mode(DCM) for power factor correction and low cost. A control method to be utilized in simulation is a average Current mode method in case of operating in CCM. The simulation results show that Better is the CCM converter then the DCM converter in harmonic content and input current waveform. And A Double-boost converter is superior to single-boost converter for input-current harmonic.

• 전자공학회논문지
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• 제50권11호
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• pp.64-69
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• 2013

본 논문에서는 10-bit 해상도의 Two-Step Single-Slope A/D 변환기를 이용한 고속 CMOS Image Sensor(CIS)를 제안하였다. 제안하는 A/D 변환기는 5-bit coarse ADC 와 6-bit fine ADC 로 구성되어 있으며, 기존의 Single-Slope A/D 변환기보다 10배 이상의 변환속도를 나타내었다. 또한 고속 동작에서 적은 노이즈 특성을 갖기 위해 Digital Correlated Double Sampling(D-CDS) 회로를 제안하였다. 설계된 A/D 변환기는 0.13um 1-poly 4-metal CIS 공정으로 제작되었으며 QVGA($320{\times}240$)급 해상도를 갖는다. 제작된 칩의 유효면적은 $5mm{\times}3mm$ 이며 3.3V 전원전압에서 약 35mW의 전력소모를 나타내었다. 변환속도는 10us 이었으며, 프레임율은 220 frames/s으로 측정되었다.

• 한국통신학회논문지
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• 제33권1A호
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• pp.85-90
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• 2008

Emitter degeneration에 의한 band SiGe HBT 이중 평형형 상향 주파수 혼합기의 선형성 개선 효과를 비교하였다. 시뮬레이션을 통해 출력 전력과 변환 이득을 동시에 고려하여 degeneration 저항값을 최적화 시켰으며 이를 $0.35{\mu}m$ Si-BiCMOS 공정을 이용하여 제작하였다. 제작 및 측정 결과, -5 dBm의 8.0 GHz LO 신호 및 100 MHz의 IF 신호 입력 시, degeneration 저항이 없는 상향 주파수 혼합기는 15.5 dB의 선형 변환 이득과 -13 dBm의 RF 출력 전력 및 3.7 dBm의 $OIP_3$를 나타내었고, degeneration 저항을 사용한 상향 주파수 혼합기는 9 dB의 선형 변환 이득과 -10 dBm의 RF 출력 전력 및 8.7 dBm의 $OIP_3$를 각각 나타내었다.