• Journal of Power Electronics
• /
• 제17권1호
• /
• pp.262-271
• /
• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• 전력전자학회논문지
• /
• 제22권3호
• /
• pp.270-275
• /
• 2017

This paper proposes a double-phase-locked-loop (PLL) to improve the performance of position estimation in hall sensor-based permanent magnet synchronous motor control. In hall sensor-based control, a PLL is normally used to estimate the rotor position. The proposed Double-PLL consists of two PLLs, including a reset type integrator. The motor control is more accurate and has better performance than conventional PLL, such as a small estimated position ripple. The validity of the proposed algorithm is verified by simulations and experiments.

• 전력전자학회논문지
• /
• 제6권6호
• /
• pp.489-497
• /
• 2001

병렬로 구성되 UPS 사이에 파라미터 불일치에 따른 순환전류와 전압리플이 발생되어지는데, 이들은 전체 UPS 시스템의 고장 및 신뢰성 저하를 유발한다. 본 논문에서는 이러한 문제점들은 Double 위상동동기기와 능동 다중인 터페이스 리액터를 사용하여 해결하였다. 또한 ADSP21061을 사용하여 제어기를 디지털적으로 구현하였다.

• Journal of Communications and Networks
• /
• 제8권1호
• /
• pp.8-12
• /
• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• 한국전자파학회논문지
• /
• 제20권9호
• /
• pp.967-973
• /
• 2009

본 논문에서는 두 개의 위상 동기 루프를 구성하여 이중으로 위상 고정시킨 band 위성통신용 국부 발진기를 설계하고 위상 잡음을 분석하였다. 설계된 위상 동기 발진기는 직렬귀환 유전체 공진발진기, 주파수 분주기, 위상검출기, 루프 필터 및 PLL-IC로 구성되어 있으며, 12.6 GHz의 발진 주파수를 2분주시켜 6.3 GHz에서 15.32 dBm의 출력값을 보였다. 제작한 발진기의 위상 잡음은 -81 dBc/Hz@100 Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz 및 -140.49 dBc/Hz@1 MHz으로 매우 안정되며 우수한 특성을 보였다.

• 전기학회논문지
• /
• 제64권9호
• /
• pp.1315-1322
• /
• 2015

This paper proposes an active islanding detection method for the BESS (Battery Energy Storage System) with 3-phase inverter which is connected to the AC grid. The proposed method adopts the DDSRF (Decoupled Double Synchronous Reference Frame) PLL (Phase Locked-Loop) so that the independent control of positive-sequence and negative-sequence current is successfully carried out using the detected phase angle information. The islanding state can be detected by sensing the variation of negative-sequence voltage at the PCC (Point of Common Connection) due to the injection of 2-3% negative-sequence current from the BESS. The proposed method provides a secure and rapid detection under the variation of negative-sequence voltage due to the sag and swell. The feasibility of proposed method was verified by computer simulations with PSCAD/EMTDC and experimental analyses with 5kW hardware prototype for the benchmark circuit of islanding detection suggested by IEEE 1547 and UL1741. The proposed method would be applicable for the secure detection of islanding state in the grid-tied Microgrid.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2018년도 추계학술대회
• /
• pp.62-64
• /
• 2018

In two-stage single-phase inverters, inherent double line frequency component is present at both input and output of the front-end converter. Generally large electrolytic capacitors are required to eliminate the ripple. It is well known that the low frequency ripple shortens the lifespan of the capacitor hence the system reliability. However, the ripple can hardly be eliminated without the hardware combined with an energy storage device or a certain control algorithm. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of the DC/AC power conversion system. The proposed control algorithm is composed of two loop, ripple rejection loop and average voltage control loop and no extra hardware is required. In addition, it does not require any information from the phase-locked-loop (PLL) of the inverter and hence it is independent of the inverter control. In order to prove the validity and feasibility of the proposed algorithm a 5kW Dual Active Bridge DC/DC converter and a single-phase inverter are implemented, and experimental results are presented.

• 대한전자공학회논문지SD
• /
• 제49권7호
• /
• pp.23-29
• /
• 2012

디지털 PLL의 핵심블록이 되는 디지털 제어 발진기를 LC 구조를 기반으로 설계하고 $0.18{\mu}m$ RF CMOS 공정을 사용하여 제작하였다. 2개의 교차쌍 구조의 NMOS 코어를 이용하여 광대역 특성을 구현하였으며, PMOS 배랙터쌍을 이용하여 수 aF의 작은 캐패시터값의 변화를 얻을 수 있었다. 캐패시터 축퇴 기법을 사용하여 캐패시턴스 값을 감소시키어 고해상도 주파수 특성을 구현하였다. 또한, 노이즈 필터링 기법을 바이어스 회로 등에 적용하여 위상잡음에 강한 구조로 설계를 하였다. 측정결과 중심주파수 2.7GHz에서 2.5GHz의 주파수 대역의 출력이 가능하였으며 2.9 ~ 7.1kHz의 높은 주파수해상도를 얻을 수 있었다. 미세튜닝범위와 코어의 전류 바이어스는 4개의 PMOS 배열을 통하여 제어가 가능하도록 하여 유연성을 높였다. 1.8V 전원에서 전류는 17~26mA 정도를 소모하였다. 설계한 DCO는 다양한 통신시스템에 응용이 가능하다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권1호
• /
• pp.126-142
• /
• 2016

This paper presents a wide-frequency-range, low-power transceiver with an automatic impedance-matching calibration for TV-white-space (TVWS) application. The wide-range automatic impedance matching calibration (AIMC) is proposed for the Drive Amplifier (DA) and LNA. The optimal $S_{22}$ and $S_{11}$ matching capacitances are selected in the DA and LNA, respectively. Also, the Single Pole Double Throw (SPDT) switch is integrated to share the antenna and matching network between the transmitter and receiver, thereby minimizing the systemic cost. An N-path filter is proposed to reject the large interferers in the TVWS frequency band. The current-driven mixer with a 25% duty LO generator is designed to achieve the high-gain and low-noise figures; also, the frequency synthesizer is designed to generate the wide-range LO signals, and it is used to implement the FSK modulation with a programmable loop bandwidth for multi-rate communication. The TVWS transceiver is implemented in $0.13{\mu}m$, 1-poly, 6-metal CMOS technology. The die area of the transceiver is $4mm{\times}3mm$. The power consumption levels of the transmitter and receiver are 64.35 mW and 39.8 mW, respectively, when the output-power level of the transmitter is +10 dBm at a supply voltage of 3.3 V. The phase noise of the PLL output at Band 2 is -128.3 dBc/Hz with a 1 MHz offset.