• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.5
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• pp.191-194
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• 2008

We will focus on the horizontal Bridgman growth system to analyze the transport phenomena numerically, because the simple furnace system and the confined growth environment allow for the precise understanding of the transport phenomena in solidification process. In conventional melt growth process, the dopant concentration tends to vary significantly along the crystal. In this work, we propose the modification of crucible geometry for improving the productivity of silicon single-crystal growth by controlling axial specific resistivity distribution. Numerical analysis has been performed to study the transport phenomena of dopant impurities in conventional and proposed Bridgman silicon growth using the finite element method and implicit Euler time integration. It has been demonstrated using mathematical models and by numerical analysis that proposed method is useful for obtaining crystals with superior uniformity along the growth direction at a lower cost than can be obtained by the conventional melt growth process.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1997.10a
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• pp.117-121
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• 1997

It is shown theoretically that uniform axial dopant concentration distribution can be made throughout the crystal by continuous Czochralski process. Numerical simulation are performed for the transient two-dimensional convection-diffusion model. A typical value of the growth and system parameters for Czochralski growth of p-type, 4 inches silicon crystal was used in the numerical calculations. Using this model with proper model parameter, the axial segregation in batchwise Czochralski growth can be described. It is studied by comparing with the experimental data. With this model parameter, the uniform axial concentration distribution of dopant is predicted in continuous Czochralski process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.5
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• pp.195-199
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• 2008

Production of the silicon feedstock for the semiconductor industry cannot meet the requirement for the solar cell industry because the production volume is too small and production cost is too high. This situation stimulates the solar cell industry to try the lower grade silicon feedstock like UMG (Upgraded Metallurgical Grade) silicon of 5$\sim$6 N in purity. However, this material contains around 1 ppma of dopant atoms like boron or phosphorous. Calculation of the composition profile of these impurities using segregation coefficient during crystal growth makes us expect the change of the type from p to n : boron rich area in the early solidified part and phosphorous rich area in the later solidified part of the silicon ingot. It was expected that the change of the growth speed during the silicon crystal growth is effective in controlling the amount of the metal impurities but not effective in reducing the amount of dopants.

• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09a
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• pp.334-335
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• 2006

WC/WC interface in VC mono-doped WC-10mass%Co submicro-grained hardmetals of $0.5\;{\mu}m$ was investigated together with WC/Co interface by using HRTEM and XMA. The thickness of V-rich layer and the analytical value of V at WC/WC interface were almost the same as those at WC/Co interfaces. These results, etc., suggested that the V-rich layers at both interfaces were not generated by an equilibrium segregation mechanism in the sintering stage, but generated by a preferential precipitation mechanism during the solidification of Co liquid phase in the cooling stage. Based on this suggestion, we succeeded in developing a nano-grained hardmetal with 100 nm $(0.1\;{\mu}m)$.

• Journal of the Korean institute of surface engineering
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• v.27 no.4
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• pp.234-240
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• 1994

A large area impurity doping method for poly-Si TFT LCD has been developed. The advantage of this method is the doping of impurities into Si over a large area without mass separation and beam scanning. Phosphorus diluted in hydrogen was discharged by RF(13.56MHz) power and ions from discharged gas were accelerated by DC acceleration voltage and were implanted into deposited Si films. The annealing characteristic of this method was similar to that of the ion implantation method in the low doping concentration. Three mechanisms were evolved in the annealing characteristics of phosphorus doped Si films. Point defects annihilation and the retrogradation of dopant atoms at grain boundaries as a result of grain growth played a major role at low and high annealing temperature, respectively. However, due to the dopant segregation, the reverse annealing range existed at intermediate annealing temperature.

• Journal of the Korean Ceramic Society
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• v.53 no.6
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• pp.635-640
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• 2016

Electrical behavior of AlN ceramics sintered with $Y_2O_3$ as a sintering aid has been investigated with respect to additional $TiO_2$ dopant. From the impedance spectroscopy, it was found that the grain and grain boundary conductivities have greatly decreased with addition of $TiO_2$ dopant. The $TiO_2$ dopant also increased the activation energy of the grain conductivity by about 0.37 eV; this increase was attributed to the formation of an associate between Al vacancies and Ti ions at the Al sites. Similarly, the electronic conductivity was reduced by $TiO_2$ addition. However, $TiO_2$ solubility in AlN grains was below the detection limit of typical EDX analysis. Grain boundary was clean, without liquid films, but did show yttrium segregation. The transference number of ions was close to 1, showing that AlN is a predominantly ionic conductor. Based on the observed results, the implications of using AlN applications as insulators have been discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1060-1067
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• 1988

In this paper, we have investigated the effects of rapid thermal process on the electrical and structural properties of silicon films. It was shown that required times and temperature for the successful activation of dopants (Boron, Phosphorus:5E15atoms/cm\ulcorner were above 1000\ulcorner, 10sec, respectively. The typical resistivities of films deposited below 600\ulcorner were in the range of 1.0 E-3ohm-cm which was 20-30% lower than that of initially polycrystalline silicon depositd above 600\ulcorner. After rapid thermal process at high temperature above 1000\ulcorner, the films did not reveal any change in resistivity due to the dopant segregation, and better electrical conductivity could be obtained by increasing the process time. The grain growth by RTA treatment was more salient in the case of the doped amorphous than that of initially polycrystalline. The surface of the films also preserved the higher structural perfection and surface smoothness.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.106-111
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• 1996

Schottky diodes are fabricated on laser annealed and unannealed polysilicon substrate and their electrical characteristics are studied and analyzed. Current of laser annealed devices are larger than that of unannealed devices because of grain growth, decrease of grain boundary and trap density, lowering of grain boundary barrier height, decrease of dopant segregation. At low forward bias (<0.7V), currents of unanealed devices are larger. Soft breakdown voltages of laser annealed devices are larger than that of unannealed devices.