• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.665-667
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• 2010

In this paper, the method to detect the IM(Inter Modulation) components of power amplifier is proposed by using frequency down-convertor. Output signals of power amplifier which is coupled by 20dB coupler and divided by power divider are applied to RF and LO of the frequency converter. It could be found the magnitude of IM components of power amplifier as a converted DC voltage which is come from the difference between 3th and 5th IM component. The detected DC voltage values are changed from 0.72V to 0.9V when 3rd IM component level changed from -26.4dBm to +2.15dBm and 5th IM component level changed from -34.2dBm to -12.89dBm as the Vgs of 3W power amplifier is changed.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.184-190
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• 2004

A feedforward linear power amplifier (FLPA) has been developed for UHF-band RFID reader applications. The main and error amplifiers are composed of a 2 stage so that linearity of the FLPA can be improved. The FLPA has been implemented on an FR-4 substrate (Er=4.7 and thickness=0.8 mm) with 3-dB and 10-dB hybrid couplers for input/output power divider and combiner. For 2-tone measurement (input level=-11 dBm at $f_1$=915 MHz and $f_2$=916 MHz), the FLPA exhibits a -18.52 dBm of $IMD_3$, which indicates that $IMD_3$ cancellation with feedforward loop is more than 27 dB. From 890 to 960 MHz, 1-dB gain compression output power and power gain of the FLPA are higher than 30 dBm and 40 dB, respectively.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.3
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• pp.326-331
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• 2010

This paper presents the design and implementation of a data acquisition system with a large number of multi-channels for manufacturing machine. The system having a throughput of 800-ch analog signals has been designed with Quartus II tool and Cyclone II FPGA. The proposed system is suitable for the large scale data handling in order to distinguish whether the operation is correct or not. The designed system is composed of a control unit, voltage divider and USB interface. To reduce the data throughput, we utilized an algorithm which can extract the same data from the achieved data. The test results of the system adapted to a manufacturing machine, show a relevant data acquisition operation of 800 channels in short time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.1
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• pp.231-238
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• 2019

In this paper, we have studied how to improve the amplifiers efficiency by minimizing the combining loss when several unit power amplifiers are combined to obtain high output power. Specifically, we have developed Ka-band Spatial Combining Amplifier. The fabricated Spatial Combining Amplifier is a Ka-band 20W class SSPA, which uses a 5W class unit amplifier module 8EA designed using a GaN bare die. We also combined The unit amplifier module using 8-way spatial divider and combiner with a hybrid radial structure. The output combining loss of the fabricated spatial coupler is about 0.334dB, which is about 92.6% efficiency. In this paper, we developed a Spatial Combining Amplifier with a maximum saturation output of 10W and a power addition efficiency of over 15%. As a result, we achieved the maximum saturation output of 30W and the power addition efficiency of 19%.

• Journal of Advanced Navigation Technology
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• v.24 no.6
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• pp.557-565
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• 2020

In order for thermal degradationIn, excore nuclear flux monitoring system, as a monitoring and signal processing methodology of reactor power, monitors neutron pulses generated during nuclear fission as frequency status, and converts them into DC voltage, and then log values resultantly. The methods realy applied in the nuclear power plant are to construct combination of counters and flip-flops, or diodes and capacitors up to now. These methodes are reliable for relative high frequencies, while not credible for reasonable low frequencies or extreme low values. Therefore, we developed the circuit that converts frequencies into DC voltages, into and into log DC values in the wide range from low Hz to several hundred high kHz. We proved their validities through testing them using real data used in nuclear power plant and analyzed their results. And, these methods will be used to measure the neutron level of excore nuclear flux monitoring system in nuclear power plant.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.3
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• pp.227-233
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• 2023

In this paper, to substitute the existing TWTA(Travailing Wave Tube Amplifier) component in small radar system, we developed the Ku band SSPA(Solid-State Power Amplifier) based on the fabrication of power MMIC (Monolithic Microwave Integrated Circuit) chips. For the development of the 500 W SSPA, the 40 W-grade power MMIC was designed by ADS(Advanced Design System) at Keysight company with UMS GH015 library, and was processed by UMS foundry service. And 70 W main power modules were achieved the 2-way T-junction combiner method by using the 40 W-grade power MMICs. Finally, the 500 W SSPA was fabricated by the wave guide type power divider between the drive power amplifier and power modules, and power combiner with same type between power modules and output port. The electrical properties of this SSPA had 504 W output power, -58.11 dBc spurious, 1.74 °/us phase variation, and -143 dBm/Hz noise level.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.2
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• pp.175-181
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• 2024

In electrical power substations, bulky iron-core potential transformers (PTs) are installed in a tank of gas-insulated switchgear (GIS) to measure system voltages. This paper proposed a low-power voltage transformer (LPVT) that can replace the conventional iron-core PTs in response to the demand for the digitalization of substations. The prototype LPVT consists of a capacitive voltage divider (CVD) which is embedded in a spacer and an impedance matching circuit using passive components. The CVD was fabricated with a flexible PCB to acquire enough insulation performance and withstand vibration and shock during operation. The performance of the LPVT was evaluated at 80%, 100%, and 120% of the rated voltage (38.1 kV) according to IEC 61869-11. An accuracy correction algorithm based on LabVIEW was applied to correct the voltage ratio and phase error. The corrected voltage ratio and phase error were +0.134% and +0.079 min., respectively, which satisfies the accuracy CL 0.2. In addition, the voltage ratio of LPVT was analyzed in ranges of -40~+40℃, and a temperature correction coefficient was applied to maintain the accuracy CL 0.2. By applying the LPVT proposed in this paper to the same rating GIS, it can be reduced the length per GIS bay by 11%, and the amount of SF6 by 5~7%.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.1-5
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• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Korean Journal of Agricultural Science
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• v.3 no.1
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• pp.95-104
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• 1976

This study was conducted to test the harvesting operation of two kinds of rice varieties such as Milyang #15 and Tong-il with a imported two furrow Japanese combine and was performed to find out the operational accuracy of it, the adaptability of this machine, and the feasibility of supplying this machine to rural area in Korea. The results obtained in this study are summarized as follows; 1. The harvesting test of the Milyang #15 was carried out 5 times from the optimum harvesting operation was good regardless of its maturity. The field grain loss ratio and the rate of unthreshed paddy were all about 1 percent. 2. The field grain loss of Tong-il harvested was increased from 5.13% to 10.34% along its maturity as shown in Fig 1. In considering this, it was needed that the combine mechanism should be improved mechanically for harvesting of Tong-il rice variety. 3. The rate of unthreshed paddy of Tong-il rice variety of which stem was short was average 1.6 percent, because the sample combine used in this study was developed on basisof the long stem variety in Japan, therefore some ears owing to the uneven stem of Tong-il rice could nat reach the teeth of the threshing drum. 4. The cracking rates of brown rice depending mostly upon the revolution speed of the threshing drum(240-350 rpm) in harvesting of Tong-il and Milyang #15 were all below 1 percent, and there was no significance between two varieties. 5. Since the ears of Tong-il rice variety covered with its leaves, a lots of trashes was produced, especially when threshed in raw materials, and the cleaning and the trashout mechanisms were clogged with those trashes very often, and so these two mechanisms were needed for being improved. 6. The sample combine of which track pressure was $0.19kg/cm^2$ could drive on the soft ground of which sinking was even 25cm as shown in Fig 3. But in considering the reaping height adjustment, 5cm sinking may be afford to drive the combine on the irregular sinking level ground without any readjustment of the resaping height. 7. The harvesting expenses per ha. by the sample combine of which annual coverage area is 4.7 ha. under conditions that the yearly workable days is 40, percentage of days being good for harvesting operation is 60%, field efficiency is 56%, working speed is 0.273m/sec, and daily workable hours is 8 hrs is reasonable to spread this combine to rural area in Korea, comparing to the expenses by the conventional harvesting expenses, if mechanical improvement is supplemented so as to harvest Tong-il rice. 8. In order to harvest Tong-il rice, the two furrow combine should be needed some mechanical improvements that divider can control not to touch ears of paddy, the space between the feeding chain and the thrshing drum is reduced, trash treatment apparatus must be improved, fore and rear adjust-interval is enlarged, and width of track must be enlarged so as to drive on the soft ground.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.