• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.946-949
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• 2004

We obtained ultra-short single pulse with an energy of 80 uJ from Distributed feedback Dye laser. Using three stages of amplifiers constructed by two stages of dye amplifiers and one bethune cell amplifier, we obtained high power pulse and second harmonic generation with BBO in ultraviolet region.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.10 s.113
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• pp.959-966
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• 2006

This paper proposes a new concept about dual band predistortion linear power amplifier(PD LPA) using diplexer for digital cellular ($f_o$=880 MHz) and IMT-2000($f_o$=2,140 MHz) base stations. The diplexer is composed of low pass filter having defected ground structure(BGS) microstrip line and high pass filter having high-Q lumped capacitors and distributed elements. The proposed predistorter adopts a reflection type intermodulation signal generator with 3 dB hybrid coupler for good reflection characteristic. for a forward link one carrier CDMA IS-95A 1FA and WCDMA 1FA signal, the proposed dual band PD LPA shows the adjacent channel leakage ratio(ACLR) improvement about 10 dB and 9.36 dB for digital cellular and IMT-2000 band, respectively.

• Journal of Power Electronics
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• v.7 no.3
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• pp.238-245
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• 2007

This paper considers the problem of regulating the output voltage of a current doubler rectified asymmetric half-bridge (CDRAHB) DC/DC converter via fuzzy integral control. First, we model the dynamic characteristics of the CDRAHB converter with the state-space averaging method, and after introducing an additional integral state of the output regulation error, we obtain the Takagi-Sugeno (TS) fuzzy model for the augmented system. Second, the concept of parallel distributed compensation is applied to the design of the TS fuzzy integral controller, in which the state feedback gains are obtained by solving the linear matrix inequalities (LMIs). Finally, numerical simulations of the considered design method are compared to those of the conventional method, in which a compensated error amplifier is designed for the stability of the feedback control loop.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.92-97
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• 2009

Low power consumption is crucial for medical implantable devices. A low-power 4th-order band-pass Gm-C filter with distributed gain stage for the sensing stage of the implantable cardiac pacemaker is proposed. For the implementation of large-time constants, a floating-gate operational transconductance amplifier with current division is employed. Experimental results for the filter have shown a SFDR of 50 dB. The power consumption is below $1.8{\mu}W$, the power supply is 1.5 V, and the core area is $2.4\;mm{\times}1.3\;mm$. The filter was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.8-16
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• 2010

An orthogonal frequency division multiplexing (OFDM) system is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower-rate subcarriers. One of the main reasons to use OFDM is to increase robustness against frequency-selective fading or narrowband interference. However, in the radio systems the distortion introduced by high power amplifiers (HPA's) such as traveling wave tube amplifier (TWTA) considered in this paper, is also critical. Since the signal amplitude of the OFDM system is Rayleigh-distributed, the performance of the OFDM system is significantly degraded by the nonlinearity of the HPA in the OFDM transmitter. In this paper, we propose a simplicial canonical piecewise-linear (SCPWL) model based digital predistorter to compensate for nonlinear distortion introduced by an HPA in an OFDM system. Computer simulation is carried on an OFDM system under additive white Gaussian noise (AWGN) channels with 16-QAM and 64-QAM modulation schemes and modulator/demodulator implemented with 1024-point FFT/IFFT. The simulation results demonstrate that the proposed predistorter achieves significant performance improvement by effectively compensating for the nonlinearity introduced by the HPA.

• ETRI Journal
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• v.27 no.5
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• pp.551-556
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• 2005

We have demonstrated a high-power widely tunable sampled grating distributed Bragg reflector (SGDBR) laser integrated monolithically with a semiconductor optical amplifier (SOA) having a lateral tapered waveguide, which is the first to emit a fiber-coupled output power of more than 10 dBm using a planar buried heterostructure (PBH). The output facet reflectivity of the integrated SOA using a lateral tapered waveguide and two-layer AR coating of $TiO_2\;and\;SiO_2$ was lower than $3\;{\times}\;10^{-4}\;over$ a wide bandwidth of 85 nm. The spectra of 40 channels spaced by 50 GHz within the tuning range of 33 nm were obtained by a precise control of SG and phase control currents. A side-mode suppression ratio of more than 35 dB was obtained in the whole tuning range. Fiber-coupled output power of more than 11 dBm and an output power variation of less than 1 dB were obtained for the whole tuning range.

• Journal of Power Electronics
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• v.13 no.1
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• pp.51-58
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• 2013

This paper proposes the power conversion mechanism of a bailer-charge-transfer zero-current-switching (CT-ZCS) circuit. The operation modes are analyzed and researched using state trajectory equations. The topology of CT-ZCS based on soft-switching inverters offers some merits such as: tracking the input reference signal dynamically, bearing load shock and short circuit, multiplying inverter N+1 redundancy parallel, coordinating power balance for easy control, and soft-switching commutation for high efficiency and large capacity. These advantages are distinctive from conventional inverter topologies and are especially demanded in AC drives: new energy generation and grid, distributed generation systems, switching power amplifier, active power filter, and reactive power compensation and so on. Prototype is manufactured and experiment results show the feasibility and dynamic voltage-tracking characteristics of the topology.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.294-297
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• 2003

This paper describes the design and the simulation of a frequency doubler for millimeter-wave applications using distributed amplifier technology. The designed frequency multiplier has 10% bandwidth at 58GHz output. This paper investigates nonlinear analysis of pHEMT frequency multipliers utilizing AM-AM and AM-PM distortion characteristics of frequency doubler. The conversion loss is 2.1dB and harmonic suppression is larger than 18.6dBc with 5dBm input power

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.2
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• pp.9-17
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• 2010

Recently, there has been much interest in orthogonal frequency division multiplexing (OFDM) for next generation wireless wideband communication systems. OFDM is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower-rate subcarriers. One of the main reasons to use OFDM is to increase robustness against frequency-selective fading or narrowband interference. However, in the radio systems it is also important to distortion introduced by high power amplifiers (HPA's) such as solid state power amplifier (SSPA) considered in this paper. Since the signal amplitude of the OFDM system is Rayleigh-distributed, the performance of the OFDM system is significantly degraded by the nonlinearity of the HPA in the OFDM transmitter. In this paper, we propose a canonical piecewise-linear (PWL) model based digital predistorter to prevent signal distortion and spectral re-growth due to the high peak-to-average power ratio (PAPR) of OFDM signal and the nonlinearity of HPA's. Computer simulation on an OFDM system under additive white Gaussian noise (AWGN) channels with QPSK, 16-QAM and 64-QAM modulation schemes and modulator/demodulator implemented with 1024-point FFT/IFFT, demonstrate that the proposed predistorter achieves significant performance improvement by effectively compensating for the nonlinearity introduced by the SSPA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.1A
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• pp.104-112
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• 2005

Some design techniques for high speed and low power pipelined 8-bit ADC are described. To perform high-speed operation with relatively low power consumption, open loop architecture is adopted, while closed loop architecture (with MDAC) is used in conventional pipeline ADC. A distributed track and hold amplifier and a cascading structure are also adopted to increase the sampling rate. To reduce the power consumption and the die area, the number of amplifiers in each stage are optimized and reduced with proposed zero-crossing point generation method. At 500-MHz sampling rate, simulation results show that the power consumption is 210mW including digital logic with 1.8V power supply. And the targeted ADC achieves ENOB of about 8-bit with input frequency up to 200-MHz and input range of 1.2Vpp (Differential). The ADC is designed using a $0.18{\mu}m$ 6-Metal 1-Poly CMOS process and occupies an area of $900{\mu}m{\times}500{\mu}m$