• 한국콘크리트학회:학술대회논문집
• /
• 한국콘크리트학회 2004년도 춘계 학술발표회 제16권1호
• /
• pp.76-79
• /
• 2004

The use of recycled aggregate concrete is increasing faster than the development of appropriate design recommendations. This paper is making advances in the recycling of waste concrete material for use as recycled aggregate to make secondary concrete product. Using recycled aggregates from demolished concrete, we manufactured concrete blocks to experiment overall performance in feasible performances. This paper reports limited experimental data on the structural performance of shear wall used concrete blocks made in recycled aggregates. Reinforced concrete frame and shear walls were tested to determine their diagonal cracking and ultimate shear behavior. The variable in the test program was the existence of infilled wall used concrete blocks Made in recycled aggregates. Based on the experimental results, Infilled wall has a high influence on the maximum strength and initial stiffness of reinforced concrete frame. Structural performance of specimen WSB1 and WSB2 is quite different from RCF specimen, particularly strength, stiffness and energy dissipation capacity.

• 대한전자공학회논문지SD
• /
• 제38권1호
• /
• pp.55-68
• /
• 2001

본 논문에서는 기존의 P(캐리전파)/G(캐리발생) 블록을 가진 ALU구조에서 발생되는 글리칭 전력소모를 최소화시킨 새로운 구조에 대해서 기술한다. 일반적으로 회로에서 발생되는 많은 글리치가 다음 단 회로로 전파될 때, 필요 없이 많은 전력소모가 발생된다. 따라서 본 논문에서는 ALU의 P/G 블록에서 발생되는 글리치를 제거하는 구조를 제안하였다. P/G블록에서 글리치가 제거되면 다음 단인 Sum 발생 블록에서 글리치에 의한 신호천이가 줄어들고, 이에 따라 전력소모가 줄어든다. P/G 블록의 출력 단에 발생되는 글리치 제거를 위해, 기존의 P/G블록내에 래치를 삽입하였다. 래치의 인에이블 신호는 P/G블록의 출력 인에이블 시간을 제어함으로써, P/G블록의 출력 단의 글리치를 제거시키는 역할을 한다. 16비트 ALU를 구현하여 HSPICE로 모의 실험한 결과, 제안한 구조는 지연시간의 증가가 거의 없으면서 약 28%의 글리칭 전력소모가 감소되었다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권1호
• /
• pp.29-34
• /
• 2015

This paper reports a couple of key circuit blocks developed for heterodyne receiver front-ends operating near 140 GHz based on SiGe HBT technology. Firstly, a 123-GHz oscillator was developed based on Colpitts topology, which showed -5 dBm output power and phase noise of -107.34 dBc/Hz at 10 MHz. DC power dissipation was 25.6 mW. Secondly, a 135 GHz mixer was developed based on a modified Gilbert Cell topology, which exhibited a peak conversion gain of 3.6 dB at 1 GHz IF at fixed LO frequency of 134 GHz. DC power dissipation was 3 mW, which mostly comes from the buffer.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권4호
• /
• pp.376-382
• /
• 2014

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is $2.99mm^2$ and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

• 해양환경안전학회지
• /
• 제25권7호
• /
• pp.834-840
• /
• 2019

최근 관광, 레저 수요의 증대로 해안 시설물(방파제)에서 낚시를 통해 여가를 즐기는 낚시객의 증대와 아울러 매년 해안 시설물인 소파블록(Tetrapod, TTP)에서의 낙상사고가 사회적 문제가 되고 있다. 본 연구에서는 낙상사고가 주로 발생하는 소파블록을 안전망으로 덮어 낚시객의 낙상을 저감하는 안전사고 방지 시설물 개발의 기초 연구로서 적절한 그물코 크기를 제시하고자 한다. 이는 안전망 시설물의 규모 및 경제성을 고려할 때 반드시 선행되어야 할 부분이다. 본 연구에서 적용한 안전망의 그물코 크기 결정 방법은 낚시객들의 성별, 연령별 현황과 한국인의 인체치수조사 결과를 바탕으로 최적의 그물코 크기를 산정하고자 하였다. 그 최종 결과로서 안전망의 그물코 크기는 최소 낚시객의 넙다리 둘레에서부터 최대 가슴둘레까지를 고려하여 18.6~27.0 cm의 범위로 산정되었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
• /
• pp.3058-3060
• /
• 2005

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications are presented. The circuit approach is based on the characteristic of the LV (Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by $0.25{\mu}m$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to ${\pm}0.5V$ with a linearity error of less than 1%. The measured -3dB bandwidth is 290MHz and the power dissipation is $37{\mu}W$. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

• 대한전자공학회논문지
• /
• 제27권8호
• /
• pp.1201-1210
• /
• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.963-966
• /
• 1999

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.

• 한국콘크리트학회:학술대회논문집
• /
• 한국콘크리트학회 2004년도 추계 학술발표회 제16권2호
• /
• pp.105-108
• /
• 2004

In general, the nonlinear behavior of composite structures composing of steel and concrete is analyzed on the basis of the assumption of the perfect bond actions in steel-concrete interface in which the interface slip or separation is not allowed. The assumption is based on the fact that the full interface bond behavior is provided with the mechanical connectors of studs. However, since the number and spacing of the studs are determined by the stress resultants calculated in the interface area, the interface analysis is required to evaluate the stress resultants. This paper describes the nonlinear steel-concrete interface behavior considering the two interface failure mechanisms of slip and separation. Elastoplastic constitutive relation is developed. thru the formulation framework using the two energy dissipation mechanisms. As the result, the steel plate push-out tests sandwitched between concrete blocks are analyzed and compared with the test results with which the good agreements are observed.

• 한국통신학회논문지
• /
• 제32권5A호
• /
• pp.503-509
• /
• 2007

저전력 움직임추정은 휴대용 정보단말의 실시간 비디오 코딩에 필수적이다. 본 논문에서는 전역탐색 블록정합 방식을 적용한 저전력 움직임추정 알고리즘과 이를 1차원 배열의 VLSI로 구현한 하드웨어 구조를 제안한다. 전역 탐색 블럭정합 방법의 전력소비의 주원인은 많은 연산량과 탐색영역의 프레임 데이터를 호출하는 횟수가 많다는 점이다. 본 논문에서는 두 개의 인접한 참조블럭의 움직임추정 연산을 동시에 병렬로 수행하여 탐색영역의 메모리 호출횟수를 감소시켰으며, 움직임추정시 결과에 영향을 미치지 않는 불필요한 연산을 제거하였다. 제안된 움직임추정 알고리즘을 1차원 PE (processing element) 배열구조의 VLSI로 구현하여 실험한 결과, 제안된 움직임추정기는 기존의 저전력 움직임추정기에 비해 9.3%의 소비전력 감소와 2배 정도의 속도향상이 있음을 확인하였다.