• 전자공학회논문지B
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• 제30B권10호
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• pp.27-34
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• 1993

In this paper, a driver system is designed and implemented to achieve 4-level gray scale CH TFEL(Thin Film ElectroLuminescent) flat panel display. To implement the driver system, commercial EL driver IC chips are used to apply high voltage pulses to the EL panel and a high voltage switching circuit is designed for the EL driver IC. A new method of reducing storage delay time of transistor is proposed to obtain a reliable switching circuit. The controller for EL driver and switching circuit is also designed. The designed driving scheme applicable to EL display with 4-level gray scale is based on the linear characteristics of brightness vs. frequency of AC TFEL. By experiment, it has been shown that the brightness of AC TEFL display with the implemented driving system is controlled by the level of gray scale.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.298-302
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• 2006

Driver electronics for emerging display technologies are presented for OLED's, microdisplays, electrophoretic displays & bi-stable LCD's. Key factors for commercialization of these technologies are derived from the experience of the LCD's, including driver IC designs, wafer and assembly processes & applications.

• 대한전자공학회논문지SD
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• 제44권6호
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• pp.83-88
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• 2007

본 논문에서는 유기발광다이오드 구동 IC의 기능을 검증하기 위하여 PLI(Programing Language Interface)를 이용한 검증방법을 제안한다. 기능 검증을 하기 위하여 HDL(Hardware Description Language) 시뮬레이터와 PLI, GUI(Graphic User Interface) 환경의 이미지 뷰어를 이용한다. 본 논문에서 제안하는 유기발광다이오드 구동 IC의 기능 검증 방법을 이용 할 경우 종래의 기능 검증 방법을 이용 할 때 보다 40배의 실행 시간 이득을 얻을 수 있다. 제안한 방법을 이용할 경우 디스플레이 구동 IC의 설계 단계에서 기능 검증을 효율적으로 할 수 있을 것이다.

• Journal of Information Display
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• 제13권2호
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• pp.73-82
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• 2012

In this paper, a light-emitting diode (LED) backlight driver integrated circuit (IC) for medium-sized liquid crystal displays (LCDs) is proposed. In the proposed IC, a linear current regulator with matched internal resistors and an adaptive phase-shifted pulse-width modulation (PWM) dimming controller are also proposed to improve LED current uniformity and reliability. The double feedback loop control boost converter is used to achieve high power efficiency, fast transient characteristic, and high dimming frequency and resolution. The proposed IC was fabricated using the 0.35 ${\mu}m$ bipolar-CMOS-DMOS (BCD) process. The LED current uniformity and LED fault immunity of the proposed IC were verified through experiments. The measured power efficiency was 90%; the measured LED current uniformity, 97%; and the measured rising and falling times of the LED current, 86 and 7 ns, respectively. Due to the fast rising and falling characteristics, the proposed IC operates up to 39 kHz PWM dimming frequency, with an 8-bit dimming resolution. It was verified that the phase difference between the PWM dimming signals is changed adaptively when LED fault occurs. The experiment results showed that the proposed IC meets the requirements for the LED backlight driver IC for medium-sized LCDs.

• 한국위성정보통신학회논문지
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• 제8권2호
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• pp.36-43
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• 2013

본 논문에서는 고전압에서 동작하는 DDIC(display driver IC) 칩의 정전기 보호소자로 사용되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커니즘이 분석되었다. 이온주입 조건을 달리하는 매트릭스 조합에 의한 수차례의 2차원 시뮬레이션 및 TLP 특성 데이타를 비교한 결과, BJT 트리거링 후에 더블 스냅백 현상이 나타났으나 웰(well) 및 드리프트(drift) 이온주입 조건을 적절히 조절함으로써 안정적인 ESD 보호성능을 얻을 수 있었다. 즉, 최적의 백그라운드 캐리어 밀도를 얻는 것이 고전압 동작용 정전기보호소자의 고전류 특성에 매우 중요한 영향을 주는 임계인자(critical factor)임을 알 수 있었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.661-662
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• 2012

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.481-487
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• 2016

A new two-line based inversion driving method is introduced for low power display-driver ICs. By inserting a timing offset between the chopper stabilization and the alternation of LCD polarity, we can reduce power consumption without noticeable degradation in the display quality. By applying the proposed scheme to 12" LCD applications, we achieved 7.5% and 27% power saving in the display-driver IC with white and black patterns, respectively.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• 반도체디스플레이기술학회지
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• 제10권3호
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• 전자공학회지
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• 제31권9호
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• pp.109-126
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• 2004