• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.124-126
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• 2013

대량의 메모리, 네트워크 장치, 저장매체, CPU 등으로 구성된 데이터 센터의 운용에 있어서 시스템 구축이나 운용을 단순화하기 위한 가상화가 고려되고 있다. 특히 금융 분야와 같이 데이터의 폭증 시대에 대응하기 위한 분산 서버 노드의 메모리 가상화 시스템을 고려할 수 있으며 본 연구에서는 이러한 메모리 가상화 시스템을 운용하는데 있어서 지연을 최소화하기 위한 인피니밴드의 활용방안에 대하여 검토한다. 인피니밴드의 메모리 접속 기능인 RDMA (Remote Direct Memory Access)를 더욱 쉽게 사용하기 위한 사용자 친화적인 라이브러리 구현 방법을 제안하며 RDMA 사용 시 발생하는 지연 현상을 분석하였다.

• ETRI Journal
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• v.44 no.3
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• pp.450-461
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• 2022

The Gen-Z protocol is a memory semantic protocol between the memory and CPU used in computer architectures with large memory pools. This study presents the implementation of the Gen-Z hardware system configured using Gen-Z specification 1.0 and reports its performance. A hardware prototype of a DDR4 Gen-Z memory pool with an optimized character, a block device driver, and a file system for the Gen-Z hardware was designed. The Gen-Z IP was targeted to the FPGA, and a 512 GB Gen-Z memory pool was configured on an ×86 server. In the experiments, the latency and throughput of the Gen-Z memory were measured and compared with those of the local memory, SATA SSD, and NVMe using character or block device interfaces. The Gen-Z hardware exhibited superior throughput and latency performance compared with SATA SSD and NVMe at block sizes under 4 kB. The MySQL and File IO benchmark of Gen-Z showed good write performance in all block sizes and threads. Besides, it showed low latency in RocksDB's fillseq dbbench using the ext4 direct access filesystem.

• The KIPS Transactions:PartD
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• v.12D no.4 s.100
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• pp.543-552
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• 2005

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. The disk-based spatial indexing techniques, however, cannot direct apply to main memory databases, because the main purpose of disk-based techniques is to reduce the number of disk accesses. In main memory-based indexing techniques, the node access time is much faster than that in disk-based indexing techniques, because all index nodes reside in a main memory. Unlike disk-based index techniques, main memory-based spatial indexing techniques must reduce key comparing time as well as node access time. In this paper, we propose an efficient spatial index structure for main memory-based databases, called Tmr-tree. Tmr-tree integrates the characteristics of R-tree and T-tree. Therefore, Nodes of Tmr-tree consist of several entries for data objects, main memory pointers to left and right child, and three additional fields. First is a MBR of a self node, which tightly encloses all data MBRs (Minimum Bounding Rectangles) in a current node, and second and third are MBRs of left and right sub-tree, respectively. Because Tmr-tree needs not to visit all leaf nodes, in terms of search time, proposed Tmr-tree outperforms R-tree in our experiments. As node size is increased, search time is drastically decreased followed by a gradual increase. However, in terms of insertion time, the performance of Tmr-tree was slightly lower than R-tree.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.445-458
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• 2007

This article presents a novel infrastructure for large-memory database processing using commodity hardware with operating system support. We exploit inexpensive PCs and a high-speed network capable of Remote Direct Memory Access (RDMA) operations to build a new memory hierarchy between fast volatile memory and slow disk storage. The new memory hierarchy guarantees a reasonable response time, and its storage size enables us to run large-memory database systems with little performance degradation. The proposed architecture has two main components: (1) a remote memory system inside the Linux kernel to manage other computers' memory pages efficiently and (2) a remote memory pager responsible for manipulating remote read/write operations on remote memory pages. We insist that the proposed architecture is practical enough to support the rigorous demands of commercial in-memory database systems by demonstrating the performance of publicly available main-memory databases (e.g., MySQL) on our prototyped system. The experimental results show very interesting results from the TPC-C benchmark.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.2
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• pp.99-107
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• 2006

Magnetic nondestructive testing is very useful far detecting a crack on the surface or near of the surface of the ferromagnetic materials. The distribution of the magnetic flux leakage (DMFL) on a specimen has to be obtained quantitatively to evaluate the crack. The magnetic camera is proposed to obtain the DMFL at the large lift-off. The magnetic camera consists of a magnetic source, magnetic lens, analog to digital converters (ADCs), interface, and computer. The magnetic leakage fields or the distorted magnetic fields from the object, which are concentrated on the magnetic lens, are converted to analog electrical signals tv arrayed small magnetic sensors. These analog signals are converted to digital signals by the ADCs, and are stored, imaged, and processed by the interface and computer. However the magnetic camera has limitations with respect to converting and switching speed, full range and resolution, direct memory access (DMA), temporary storage speed and volume because common ADCs were used. Improved techniques, such as those that introduce the operational amplifier (OP-Amp), amplify the signal, reduce the connection line, and use the low pass filter (LPF) to increase the signal to noise ratio are necessary. This paper proposes the exclusive embedded ADC including OP-Amp, LPF, microprocessor and DMA circuit for the magnetic camera to satisfy the conditions mentioned above.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.5
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• pp.32-37
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• 1982

This paper shows a design method of English/Hanguel/Chinese display controller using address conversion thchnique and DMA in the raster scanning graphic CRT display by giving a design example (64 characters$\times$16 lines display controller).

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.63-66
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• 2001

본 논문에서는 TI사의 TMS320C6201 DSP를 이용하여 H.263 동영상 부호화기를 실시간 구현하고자 한다. 구현한 부호화기는 QCIF 형식의 영상을 사용하여 ITU-T H.263 권고안의 기본 모드를 따라 주로 C 언어와 intrinsics를 사용하여 구현하였다. 특히, 속도 향상을 위해서 고속 메모리의 사용을 극대화하는데 중점을 두었고, 연산량이 많은 모듈에 대한 최적화와 데이터의 병렬 처리 및 DMA (Direct Memory Access) 전송 등을 고려하여 구현하였다.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.493-496
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• 2000

본 논문에서는 TMS320C6201 DSP (Digial Signal Processor)를 이용하여 실시간 영상 부호화기를 구현하였다. 기본적인 영상 압축 방법으로는 baseline-JPEG을 사용하였고 이에 움직임 검출 알고리즘을 부가하여 영상의 시간적인 중복성을 제거하였다. 특히 저속 메모리와 고속 메모리의 효율적인 분배 사용, 계산량이 많은 모듈의 최적화, 데이터의 병렬 연산과 DMA (Direct Memory Access)를 이용한 데이터 전송 등의 방법을 통하여 실시간 영상 부호화기의 고속 영상 처리에 중점을 두었다.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.687-688
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• 2006

This paper presents implementation of the lifting based DWT processor interface which the process of JPEG2000. The proposed architecture uses Excalibur device produced Altera. This study describes CIS(CMOS Image Sensor), DMA(Direct Memory Access) and DWT control logic