• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1586-1592
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• 2017

Voltage sourced converter (VSC) based direct-current (DC) grid has the ability to control power flow flexibly and securely, thus it has become one of the most valid approaches in aspect of large-scale renewable power generation, oceanic island power supply and new urban grid construction. To solve the optimal power flow (OPF) problem in DC grid, an adaptive particle swarm optimization (PSO) algorithm based on fuzzy control theory is proposed in this paper, and the optimal operation considering both power loss and voltage quality is realized. Firstly, the fuzzy membership curve is used to transform two objectives into one, the fitness value of latest step is introduced as input of fuzzy controller to adjust the controlling parameters of PSO dynamically. The proposed strategy was applied in solving the power flow issue in six terminals DC grid model, and corresponding results are presented to verify the effectiveness and feasibility of proposed algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.12
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• pp.2311-2315
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• 2009

This paper presents a method to apply energy margin for assesment of total transfer capability (TTC). In order to calculate energy margin, two values of the transient energy function have to be computed. The first value is transient energy that is the sum of kinetic and potential energy at the end of fault. The second is critical energy that is potential energy at controlling UEP(Unstable Equilibrium Point). It is seen that TTC level is determined by not only bus voltage magnitudes and line thermal limits but also transient stability. TTC assessment is compared by the repeated power flow(RPF) method and optimization method.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.1-6
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• 1997

This paper describes the design of a network interface controller (NIC) chip which is to be used to support a novel adaptive virtual cut-through routing method for parallel compute systems with direct (i.e., point-to-point) interconnection networks. The NIC chip is designed to provide the interface between a processing node constructed from commercially available microprocessors and another custom-designed router chip, which in turn performs the actual routing of packets to their respective destinations. The NIC, designed using a semi-full-custom VLSi design technique outperform traditional wormhole routing with a minimal amount of hardware overhead. The NIC design has been fully simulated and laid out using a 0.8$\mu\textrm{m}$ CMOS process.

• Transactions on Electrical and Electronic Materials
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• v.3 no.4
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• pp.5-9
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• 2002

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. Especially, to achieve the higher density and greater performance, shallow trench isolation (STI)-CMP process has been attracted attention for multilevel interconnection as an essential isolation technology. Also, it was possible to apply the direct STI-CMP process without reverse moat etch step using high selectivity slurry (HSS). In this work, we determined the process margin with optimized process conditions to apply HSS STI-CMP process. Then, we evaluated the reliability and reproducibility of STI-CMP process through the optimal process conditions. The wafer-to-wafer thickness variation and day-by-day reproducibility of STI-CMP process after repeatable tests were investigated. Our experimental results show, quite acceptable and reproducible CMP results with a wafer-to-wafer thickness variation within 400$\AA$.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.7-13
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• 2019

Power module is getting attention from electronic industries such as solar cell, battery and electric vehicles. Transient liquid phase (TLP) boding, sintering with Ag and Cu powders and wire bonding are applied to power module packaging. Sintering is a popular process but it has some disadvantages such as high cost, complex procedures and long bonding time. Meanwhile, TLP bonding has lower bonding temperature, cost effectiveness and less porosity. However, it also needs to improve ductility of the intermetallic compounds (IMCs) at the joint. Wire boding is also an important interconnection process between semiconductor chip and metal lead for direct bonded copper (DBC). In this study, TLP bonding using Sn-based solders and wire bonding process for power electronics packaging are described.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.1-10
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• 2009

Carbon nanotube(CNT)s have been considered as one of the most unique materials due to the their superior mechanical, thermal and electrical properties. Therefore, numerous studies have been performed for the utilization of CNTs. This review article focuses on the recent research trends on the utilization of CNTs for new interconnect materials in electronics packaging. Major contents mentioned are the direct interconnection technology using CNTs and the main properties of polymer/CNTs composite materials. This article is aimed at the reviewing of important results from the recent studies and providing the straightforward understanding of the results through the mutual analysis and a industrial viewpoint.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.3
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• pp.105-112
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• 2017

PCI Express is a bus technology that connects the processor and the peripheral I/O devices that widely used as an industry standard because it has the characteristics of high-speed, low power. In addition, PCI Express is system interconnect technology such as Ethernet and Infiniband used in high-performance computing and computer cluster. PGAS(partitioned global address space) programming model is often used to implement the one-sided RDMA(remote direct memory access) from multi-host systems, such as computer clusters. In this paper, we design and implement a OpenSHMEM API based on PCI Express maintaining the existing features of OpenSHMEM to implement RDMA based on PCI Express. We perform experiment with implemented OpenSHMEM API through a matrix multiplication example from system which PCs connected with NTB(non-transparent bridge) technology of PCI Express. The PCI Express interconnection network is currently very expensive and is not yet widely available to the general public. Nevertheless, we actually implemented and evaluated a PCI Express based interconnection network on the RDK evaluation board. In addition, we have implemented the OpenSHMEM software stack, which is of great interest recently.

• Journal of Korean Society on Water Environment
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• v.24 no.6
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• pp.767-772
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• 2008

Studies regarding the application of the impervious cover rate as a watershed management index have increased in number due to concerns over watershed management. The impervious cover rate is suggested as an index that can manage not only water quality but also water volume and the water ecosystem. This study intends to prove its applicability through the interconnection of the impervious cover rate and the water environment in Korea. Analysis of a selected watershed with reference to impervious cover rates showed that a watershed with an impervious cover rate of over 30% had a direct runoff in excess of 60% of precipitation, while a watershed with an impervious cover rate of 7% had a direct runoff of 39%. Watersheds with higher impervious cover rates were also found to have higher BOD, though different watersheds showed slightly different aspects in connection with BOD. Monitoring of benthic macroinvertebrates showed that species inhabiting clean water appear more frequently in areas with lower impervious cover rates than areas with higher impervious cover rates, and in mainstream areas, relatively larger numbers of species appeared in areas with lower impervious cover rates. This suggests that impervious cover rates can be appropriately used as an index for watershed management, as it effectively represents changes to the water environment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.11
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• pp.1408-1414
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• 2018

Recently, as a solution to the problem of maintaining system reliability, stability, and quality occurring worldwide, such as activation of smart grid and recognition of super grid and rapid grid interconnection of renewable energy sources HVDC(High Voltage Direct Current) will appear on the front of the electric power system. These concepts are also very important concepts in HVDC systems. When the HVDC system is linked to the existing power system, it is composed of AC/DC/AC conversion device, and these conversion devices are composed of many thyristors. These parts(Devices) are connected in a complicated manner, and they belong to the one with a higher failure rate. However, the problem of establishing the concept of failure rate of HVDC parts directly linked to economic efficiency and the understanding accompanying it are still insufficient. Therefore, in this paper, we establish the meaning of reliability in power system and try to develop a model to analyze and verify the failure rate data of HVDC based on this.