• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1053-1056
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• 2005

This paper proposes a design technique of DDS (Direct Digital Synthesizer) to reduce the ROM size, and also describes the procedure of the implementation of the technique. Unlike other techniques suggested so far, the proposed technique is able to reduce the ROM size to a great extent with minimal hardware overheads. The frequencies of the signal synthesized by the implemented DDS accurately changed with the applied frequency control words.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.771-776
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• 2014

In this paper, an agile programmable chirp spread spectrum generator for wideband frequency-jamming applications from 20 MHz to 3 GHz is proposed. A frequency-mixing architecture using two voltage-controlled oscillators is used to achieve a wideband operating frequency range, and the direct digital synthesizer (DDS)-based chirping method with a two-point modulation technique is employed to provide a programmable and consistent chirp bandwidth. The proposed signal generator provides the various programmable FM signals from 20 MHz to 3 GHz with a modulation bandwidth from 0 to 400 MHz. The prototype successfully demonstrates arbitrary sequential jamming operation with a fast band-to-band hopping time of < 10 ${\mu}sec$.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.3
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• pp.41-51
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• 1997

In this study, two types of the direct digital frequency synthesizers (DDFS) designed and implemented using 1.0.mu.m CMOS gatearray(SOG) technolgoies are interoduced. To analize the effect of the number of phase bits(L), address data bits(A), and DAC bits (D) on the output spectrums of the DDFSs, the NCO-based BCD-DDFS composed of L=24, A=14, and D=8, and the improved binary-DDFS composed of L=24, A=8, and D=10 have been studied. The chips have been designed with and without a noise shapper to reduce spurious noises due to phase truncation and reduced sine ROM in output spectrum.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.321-330
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• 2010

In this paper, the theoretical background and the specific implementation method of a compressive receiver for RFID signal detection as well as the design method of DDL(Dispersive Delay Line) and chirp LO are described. DDL, which is one of the main components of the compressive receiver, is designed to have $13{\mu}s$ dispersive delay time and 6 MHz bandwidth using the SAW technique based on $LiNbO_3$ material. The chirp LO is designed using DDS(Direct Digital Synthesizer). Also the compressive receiver is fabricated to be installed into the RFID reader. Test results show the maximum frequency error of 25 kHz for single signal input, the receiver sensitivity of -44 dBm, and the maximum frequency error is 75 kHz for 6 multi-tone input signals. These results indicate that the fabricated compressive receiver is working well even in dense RFID operating environments.

• Journal of the Korea Institute of Military Science and Technology
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• v.19 no.3
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• pp.379-386
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• 2016

In this paper, phase noise analysis result for 2.4 GHz PLL(phase locked loop) using SPD(sample phase detector) is proposed. It can be used for high performance frequency synthesizer's LO(local oscillator) to extend output frequency range or for LO of offset PLL to reduce a division rate or for clock signal of DDS(direct digital synthesizer). Before manufacturing, theoretical estimation of PLL's phase noise performance should be performed. In order to calculate phase noise of PLL using SPD, Leeson model is used for modeling phase noise of VCO(voltage controlled oscillator) and OCXO(ovened crystal oscillator). After theoretically analyzing phase noise of PLL, optimized loop filter bandwidth was determined. And then, phase noise of designed loop filter was calculated to find suitable OP-Amp. Also, the calculated result of phase noise was compared with the measured one. The measured phase noise of PLL was -130 dBc/Hz @ 10 kHz.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.1-7
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• 1997

In tis paper, w eproposed a modeling for direct-sequence spread communication base band modem in RT-level VHDL and implemented in a one-chip VLSI and tested. The transmitter modulates with DQPSK modulation method and spreads a modulated signal with 32-bit PN code into 1.152MHz. The receiver de-spreads a signal using 32-tap matched filter and recovers with DQPSK demodulation method. The digital frequency synthesizer generates the sine signal and the cosine signal of 2.304MHz with ROM tables in the size of 7$\^$*/256 and 6$\^$*/256, respectively. The implemented VLSI has been verified a BER with 10$\^$-4/ at E$\_$b//N$\_$o/ of 13dB with a SPW fixed design model and fabricated in the 0.8.mu.m KG6423 gate array with a VHDL model.

• Journal of the Korea Computer Industry Society
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• v.2 no.8
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• pp.1063-1068
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• 2001

In this paper, we designed a high resolution six channel DSB modulator of Acousto-Optic effect generator make use of DDS technology. Also, configured seamless connection for other instruments to use IEEE-488 bus interface. We programmed the device driver for DDS and DAC control by 80C51 assembler language. And, high resolution 6 channel DSB modulator has improved the important characteristics of that the frequency tuning range, the resolution, the switching time. This DSB modulator system can use high precision frequency synthesizer for instruments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.615-618
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• 2006

The broadband power detector for direct- onversion Six-port output circuit was designed and implementaed in this paper. The power detector should linearly operated to produce the linear amplitude and phase signal fer input RF signal in required broadband. So, the power detector should be designed under conditions of matching circuit with low VSWR. The designed power detectors, which were implemented in L-band with 50 ohm matching and Ku-band with matching circuit and isolator, respectively, were evaluated in the performances.

• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.