• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.2
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• pp.302-312
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. Double frequency conversion and active tracking filter was used in order to suppress IF beat and image band, which results in reducing the interference between adjacent channels and multi-channels. The implemented digital TV tuner has excellent performance such as the wide dynamic range, good flatness in passing band, and low phase noise. The developed tuner is available to handle the digital and analogue television signal at the same time.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.951-954
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• 2001

본 논문에서는 SDR (Software Defined Radio)시스템을 위한 디지털 IF (Intermediate Frequency)수신기를 구현하였다[1][2]. 구현된 수신기의 하드웨어 구조는 AD변환부, PDC(Programmable Down Converter)부, DSP (Digital Signal Processing)부분으로 이루어졌다. AD변환부는 Analog Devices사의 AD6644를 이용하여 아날로그 신호를14bit의 디지털 신호로 변환된다. PDC부분은 Intersil사의 HSP 50214B를 이용하여 14bit 샘플 된 IF(Intermediate Frequency)입력을 혼합기와 NCO(Numerically Controlled Oscillator)에 의해 기저대역으로 다운 시키는 역할을 한다. PDC는 CIC (Cascaded Integrator Comb)필터, Halfband 필터 그리고 프로그램할 수 있는 FIR필터로 구성되어 있다. 그리고 PDC부분을 제어하고 PDC부분에서 처리할 수 없는 캐리어, 심볼 트래킹을 위해 Texas Instrument사의 16비트의 고정소수점 DSP인 TMS320C5416과 Altera사의 FPGA를 사용하였다. 그러므로 중간주파수 대역과 기저대역 간의 신호변환을 디지털 신호처리를 수행함으로써 일반적인 아날로그 처리방식보다 고도의 유연성과 고성능 동작이 가능하고 시간과 환경 변화에 우수한 동작 특성을 제공한다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.104-107
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• 2000

We designed and implemented the RFIC(RF front-end IC) for DTV(Digital TV) tuner. The DTV tuner RF front-end consists of low noise IF amplifier fur the amplification of 900 MHz RF signal and down conversion mixer for the RF signal to 44MHz IF conversion. The RFIC is implemented on ETRI 0.8u high resistive (2㎘ -cm) and evaluated by on wafer, packaged chip test. The gain and IIP3 of IF amplifier are 15㏈ and -6.6㏈m respectively. For the down conversion mixer gain and IIP3 are 13㏈ and -6.5㏈m. Operating voltage of the IF amplifier and the down mixer is 5V, current consumption are 13㎃ and 26㎃ respectively.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.4
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• pp.8-17
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• 1999

In this paper, a proposal for improving the performance of IF in-phase combiner is presented in view of simple hardware design and good performance for space diversity application. By adding the stable normalization circuit to the phase detector, better performances are obtained even for a severe notch depth of 30 dB. To check the validity of this proposal, various results based upon numerical simulation and laboratory test are presented here in conjunction with 64-QAM digital radio relay system.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2006.11a
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• pp.7-10
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• 2006

지능형 디지털 재설계 기법의 중요한 가정은 퍼지 IF-THEN 규칙의 발화도가 샘플링 구간에서 샘플링 순간의 값으로 근사화 된다는 점이다. 본 논문은 퍼지 IF-THEN 규칙 발화도의 근사화 가정을 배제한 경우에 대하여 기존의 지능형 디지털 재설계 기법에 의하여 재설계된 디지털 제어기의 안정화 가능성을 조사한다.

• Proceedings of the Korea Multimedia Society Conference
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• 2004.05a
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• pp.293-297
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• 2004

Recently, with the spread of digital camera and PC cam, need of tools for display and manipulation of digital images have increased remarkably. These tools are called as digital album. Af now, people want to see picture not alone in home but share with someone else. The purpose of this study is to develop a digital album, which is easy to use, easy to approach and has more function. Therefore people can see picture everywhere he want and management it. If computer is connected In Internet.

• The Journal of Society for e-Business Studies
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• v.5 no.1
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• pp.135-158
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• 2000

In recent years, many retail businesses jumped on the Internet auction bandwagon and paid substantially high fees to learn and develop proper business strategies for this new environment. Unlike what most businesses in the real world presume, this research shows that discriminatory-price ascending-bid auctions in a digital economy might be not very beneficial for the sellers on the Internet, if sellers sell the identical digital products through both a typical posted-price market and an auction. Using an extensive technology infrastructure along with suitable incentives and rules for market agents, we found that a discriminatory-price ascending-bid auction, which is the most popular auction mechanism on the Internet, serves consumers better than it does the sellers or producers in the digital economy. That is, the average prices for digital goods in these auctions are substantially lower than the prices in a posted-price market. This shows that it is not so wise for sellers to jump on the bandwagon of Internet auctions, if there is a market place with posted-price mechanisms which sells comparable items, or if a seller does not have special advantages or strategies in this new market institution. Electronic market mechanisms provide powerful means of understanding and measuring consumer characteristics including willingness-to-pay and other demographics for sellers or producers. Many concern that sellers may extract the entire surplus from the market by using customization on the Internet, thus consumers will be worse off in this digital economy. We found that these sellers who can customize their products and prices fail to capture the whole consumers surplus and cannot exercise a monopoly. One major explanation for this phenomenon is that the competition among the sellers prohibits them from charging prices according to customers demand for each product, where switching from one seller to another is not so difficult for the customers, and reselling products among the buyers are prohibited.

• Journal of the Institute of Convergence Signal Processing
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• v.19 no.4
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• pp.153-161
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• 2018

This paper describes the performance improvement of Software (SW) digital filter using GPU (Graphical Processing Unit). The previous developed SW digital filter has a problem that it operates on a CPU (Central Processing Unit) basis and has a slow speed. The GPU was introduced to filter the data of the EAVN (East Asian VLBI Network) observation to improve the operation speed and to process data with other stations through filtering, respectively. In order to enhance the computational speed of the SW digital filter, NVIDIA Titan V GPU board with built-in Tensor Core is used. The processing speed of about 0.78 (1Gbps, 16MHz BW, 16-IF) and 1.1 (2Gbps, 32MHz BW, 16-IF) times for the observing time was achieved by filtering the 95 second observation data of 2 Gbps (512 MHz BW, 1-IF), respectively. In addition, 2Gbps data is digitally filtered for the 1 and 2Gbps simultaneously observed with KVN (Korean VLBI Network), and compared with the 1Gbps, we obtained similar values such as cross power spectrum, phase, and SNR (Signal to Noise Ratio). As a result, the effectiveness of developed SW digital filter using GPU in this research was confirmed for utilizing the data processing and analysis. In the future, it is expected that the observation data will be able to be filtered in real time when the distributed processing optimization of source code for using multiple GPU boards.

• Journal of information and communication convergence engineering
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• v.9 no.5
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• pp.615-618
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• 2011

Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to found the error quickly. Self-repairing of digital systems as an advanced form of fault-tolerance has been increasingly receiving attention according as digital systems have been more and more complex and speed-up especially for urgent systems or those working on extreme environments such as deep sea and outer space. Simulating the process of cell differentiation algorithm was confirmed by the FPGA on the counter circuit. If an error occurs on the circuit where the error was quickly locate and repair. In this paper, we propose a novel self-repair architecture for fast and robust fault-recovery that can easily apply to real, complex digital systems. These Self-Repairing Algorithms make it possible for the application digital systems to be alive even though in very noisy and extreme environments.

• The Journal of the Korea institute of electronic communication sciences
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• v.1 no.1
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• pp.8-19
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• 2006

The RF Module which can be adjusted for a digital terrestrial and multi standard(DVB-C, ISDB-T, DVB-H) reception is developed. The Module by single conversion does divide a broadband(45MHz~860MHz) broadcasting channels into three-bands(UHF, VHF_HIGH, VHF_LOW) to satisfy some electrical performances such as image signal rejection, phase noise, IF flatness etc and digital reception specifications such as analog and digital adjacent channel protection, co-channel protection which is important in environment with co-existence both analog and digital broadcasting systems.