• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.155-167
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• 2015

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a $0.13{\mu}m$ process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

• Journal of Broadcast Engineering
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• v.9 no.4 s.25
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• pp.283-296
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• 2004

TV-Anytime metadata can be delivered by unidirectional or bi-directional network. In bi -directional environment, the special request of a client is sent to metadata service providers and then the providers provide the personalized metadata back to the client. In this paper. we introduce the design and implementation of a broadcasting receiver for personalized broadcasting service in bi-directional environment. We describe actual system configuration and usage examples for bi-directional personalized service. The implemented receiver provides various functions for a digital broadcasting recorder and is based on TV-Anytime specification and UDDI specification to provide the metadata service discovery.

• ETRI Journal
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• v.44 no.5
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• pp.859-874
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• 2022

This paper presents a low-power and lightweight human body communication (HBC) receiver with an embedded dummy electrode for improved signal acquisition. The clock data recovery (CDR) circuit in the receiver operates with a low supply voltage and utilizes a clock phase inversion scheme. The receiver is equipped with a main electrode and dummy electrode that strengthen the capacitive-coupled signal at the receiver frontend. The receiver CDR circuit exploits a clock inversion scheme to allow 0.9-V operation while achieving a shorter lock time than at 3.3-V operation. In experiments, a receiver chip fabricated using 130-nm complementary metal-oxide-semiconductor technology was demonstrated to successfully receive the transmitted signal when the transmitter and receiver are placed separately on each hand of the user while consuming only 4.98 mW at a 0.9-V supply voltage.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2003.11a
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• pp.187-190
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• 2003

In this paper, the efficient implementation technique of media processing part in the terrestrial and satellite DMB (Digital Multimedia Broadcasting) receiver is presented. To implement the unified multimedia Processor of DMB receiver, we investigated the characteristic of DMB service and the functionality of each processing part in the DMB receiver. To implement the synchronization between audio and video media, we present the general method to use the reference clock of the stream in the DMB receiver. Also we present the method to handle the bit error of the received bitstream within the wireless net work for robust media processor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.12
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• pp.986-991
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• 2018

In this paper, an A/D conversion module was designed and fabricated to improve the dynamic range of wideband digital receivers. The A/D conversion module for expanding the dynamic range converts signals into a digital signal by branching the input signal into the normal path and the amplification path according to the input signal level. Test results of the fabricated module show that the normal path of the A/D conversion module converts an input level of -57 dBm to -12 dBm into a digital signal, and the amplification path converts an input level of -30 dBm to +12 dBm into a digital signal without distortion. This translates to an input dynamic range characteristic of 69 dB. Moreover, it is confirmed that the constant output characteristic is exhibited at an instantaneous bandwidth of 100 MHz.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.139-142
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• 1998

This paper presents a method to determine the rolloff factors of both the digital terrestrial TV modulator and the bandpass filter (BPF) at the digital TV receiver input, using an analytical power spectral density model satisfying given co-channel and adjacent channel protection ratios for the digital terrestrial broadcasting services. Since the proposed method is very simple and effective to use, also can be used regardless of type of systems or modulation techniques, this method is expected to be applied to select some other digital terrestrial broadcasting system specifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.3
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• pp.296-303
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• 2003

In this paper, a design method is proposed for the reflection type phase shifter applied to the DTV(Digital TV) receiver, and a phase shifter is designed by using the design equations to satisfy the phase shifting range over 180 degrees for frequency range from 470 MHz to 860 MHz, the receiving band of DTV. From the proposed method, it is possible that the systematic design of the reflection type phase shifter with desired phase shifting range and insertion loss. In addition, it is found that the realized phase shifter satisfies the given specifications.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.111-118
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• 2013

This paper presents implementation of Air protocol analyzer and physical layer design algorithm. The analyzer is a measurement system providing real-time analysis of wireless signals between User Equipment (UE) and Node-B. The implemented system proposed in this paper consists of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The waveform of Wideband Code Division Multiple Access (WCDMA) has been selected for verification of the proposed system. We designed the analyzer using equalizer algorithm and rake-receiver algorithm. Among various algorithms of designing the equalizer, we have chosen Linear Minimum Mean Square Error (LMMSE) equalizer that uses the inverse of channel matrix. Since the LMMSE equalizer uses the inverse channel matrix, it suffers from a large amount of computational load, while it outperforms most conventional equalizers. In this paper, we introduce an efficient procedure of reducing the computational load required by LMMSE equalizer-based receiver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6A
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• pp.426-437
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• 2012

This paper proposes an array antenna assisted Doppler spread compensator with dummy elements which are placed on either end of a monopole array for a digital terrestrial television broadcasting (DTTB) receiver. An array antenna assisted Doppler spread compensator, proposed previously, has a major drawback in performance degradation owing to mutual coupling effect among array elements. In order to solve the mutual coupling problem, dummy elements, placed on both sides of the monopole array mitigate performance degradation of a Doppler spread compensator arising from the mutual coupling among monopole array elements. Computer simulation results show that the dummy elements can reduce this performance degradation as well as expand the operating bandwidth of a Doppler spread compensator.

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.