• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 1998.11a
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• pp.162-165
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• 1998

A certain degree of energy saving can be possible by controlling the delay time of occupancy sensor. In this paper a control circuit is designed for automatic control of delay time setting appropriate to different situations using a digital counter, two latches and an adder. The delay time is controlled by adjusting the time constant of RC circuit through on-off control of switching devices according to adder output, which determines the base current level of switching devices. And from PSpice simulation it is verified to function properly.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.6
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• pp.1-6
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• 1976

In this paper, the methode of calculating conversion loss is proposed by considering the thickness of bonding medium between electrode and delay material in the vibrator of Elastic delay lines. As the result of computations using digital computer, it is shown that the thickness of bonding medium must be less than about 1/100 of the thickness of vibrator and when the thickness of electrode is about 1110 of vibrator, the center fnequency is shifted. When the thickness of bonding medium is equal to or more than the thickness of vibrator, the 리uctuations in frequency Bandwidth become larger and larger.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.163-170
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• 2007

In this paper, we propose that the polyphase scaler whose performance to that of the bicubic method, has less complexity in hardware structure. In order to get the new information, proposed system is based on the group delay which is one of the digital filter characteristics. The performance of this system is superior to that of bicubic algorithm which is well known. Because the hardware structure is simpler than other image scalers, we can adopt this system for mobile devices easily. The previous polyphase filters make blurring noise which is generated by up-scaling. We replace polyphase filters by boost-up filter to get vivid image. The proposed scaler is verified by Xilinx Virtex2 FPGA and is used as digital Boom in mobile camera phone.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.93-96
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• 2000

This paper has been proposed an audio DAC structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter on-a-chip. The passband ripple(< 0.41${\times}$fs), passband attenuation(at 0.41${\times}$fs) and stopband attenuation(> 0.59${\times}$fs) of the Δ$\Sigma$ modulator output using the proposed digital interpolation filter had ${\pm}$ 0.001 ［㏈］, -0.0025［㏈］ and -75［㏈］, respectively. Also the inband group delay was 30.07/fs［s］ and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20［㏈］ approximately at 65［㎑］, out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2593-2596
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• 2003

The deadbeat properties have been well known in designing digital control systems. But recently several researchers proposed a CDBC(Continuout-time DeadBeat Controller) in continuous time. They used delay or smoothing elements from the finite Laplace Transform. A delay element is made by the exponential terms. A smoothing element is used to smooth the digital control input. And eventually the process is argumentd with smoothing elements and then well-known digital deadbeat controller is designed Sometimes samplings are done in continuous time systems and some hold devices are used to relate to digital systems. So multirate sampling may enhance the efficiency of the CDBC. A DC servo motor is chosen for implementing CDBC algorithm. Especially Outputs according to the variable input and disturbance are simulated. by use of Matlab Simulink.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.8 no.2
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• pp.41-45
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• 1994

In this paper, it is implemented that Sub- MRA PWM techinque which is applied to MRA PWM technique using the Digital Signal Processor. Unstable element of analog is reduced for Sub - MRA PWM technique by digital signal pressing. And harmonic is analized by simulation to verify that. It is afford the process induction motor control with real time by minimizing the delay time of digital system. Time delay which is a defect of digital control can by minimized using fast caculation. Therefore, real time control is implemented in the induction motor

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2043-2054
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• 1996

In this paper, Digital Delay Locked Loop(DDLL) is designed, implemented and analysed by experiment whose results show that it is possible to track the received signal by this scheme. Designed digital DLL has an advantage that it is not needed to maintain gain balance between early and late channels, which has been problem with an analog DLL. Also DDLL has more improved noise performance compared to analog DLL due to noise level limitation and noise cancellation characteristics. For various loop parameters, their effects on loop performance are analysed and simulated. Proposed DDLL is the first attempt as a digital approach in code tracking loop and it is expected to be a good reference for spread spectrum communication research.

• Journal of Korea Multimedia Society
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• v.25 no.2
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• pp.325-334
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• 2022

Digital twin has the advantages of quality improvement and cost reduction, so it is widely applied to various industries. In this paper, a method to implement the major technologies of digital twin easily and quickly is presented. These include data management and relay servers, real-time monitoring applications including remote control interfaces, and direct connection protocols for video streaming. In addition, an algorithm for controlling a two-wheeled vehicle with a 2D interface is also proposed. The implemented system performs near real-time synchronization between the real environment and the virtual space. The delay time that occurs in remote control of the vehicle in the real environment was compared with the results of applying the proposed delay time reduction method. In addition, in the case of 2D interface-based control, an algorithm that can guarantee the user experience was implemented and applied to the actual environment and verified through experiments.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.