• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2376-2385
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• 1994

In receiving the digital TV signal, both decoding delay and the channel hopping delay are very critical factors in applications. The intra-slice coding in the MPEG-2 SIMPLE PROFLE of No B-picture is one of the primary methods for short delay time in video decoding. It has the advantage of short decoding delay, but has the drawback of long channel hopping delay time. In this paper, we propose a method to reduce the channel delay with negligible loss in SNR performance. It is shown that dividing pictures into several regions of slices and adding some restriction in motion vector search for inter-frame coding. hence the random acess points are effectively increased. and the channel hopping delay is reduced.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.34 no.2
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• pp.63-71
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• 1985

The existing methods of pole assignment were reserved in this paper, a digital control method for MIMO dynamic systems was developed based on pole assignment using I/O delay. The underlined concept of the derived control law was that the poles corresponding to the order of a system can be assigned on the desired positions via output delay, and the poles of the order incrememted by output delay were forced to be placed on zero positions by way of input delay when applied to an actual MIMO system, the present scheme was shown to be more effective than the conventional state feedback scheme with observer in that the former was simpler than the latter, while they performed well.

• Journal of Digital Contents Society
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• v.9 no.4
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• pp.679-686
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• 2008

Wireless LAN(WLAN) is a rather mature communication technology connecting mobile terminals. IEEE 802.11 is a representative protocol among WLAN technologies. With the rising popularity of delay-sensitive real-time multimedia applications(video, voice and data) in IEEE 802.11 wireless LAN, it is important to study the MAC layer delay performance of WLANs. In this paper, performance for packet delay model that recently have been proposed schemes is analysed in wireless LAN and proved performance results via simulation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.47-53
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• 2012

Sensor networks and car networks that have different structure from that of conventional TCP/IP network require extreme network environment due to frequent change of connectivity. Because such extreme network environment has characteristics like unreliable link connectivity, long delay time, asymmetrical data transfer rate, and high error rate, etc., it is difficult to perform normally with the conventional TCP/P-based routing. DTNs (delay and disruption tolerant network) was designed to support data transfer in extreme network environment with long delay time and no guarantee for continuous connectivity between terminals. This study suggests an algorithm that limits the maximum number of copying transferred message to L by improving the spray and wait routing protocol, which is one of the conventional DTNs routing protocols, and using the azimuth and density data of the mobile nods. The suggested algorithm was examined by using ONE, a DTNs simulator. As a result, it could reduce the delay time and overhead of unnecessary packets compared to the conventional spray and wait routing protocol.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.8
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• pp.1444-1454
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• 2000

The implementation of IF group delay equalizer and its performance are presented for radio relay system applications, and measured results are in good agreement with the simulated ones based upon analytical formulations. For waveguide filter of 40㎒ channel spacing, equalized delay accuracy of about +/- 2.0nsec can be obtained only by constructing 4 stage delay circuits, which provides good performance in system BER curves compared with no filter case, and the difference is less than 1.0㏈ at $10^{-12}$ BER. So this scheme with simple hardware design can be used for correcting the distorted group delays mainly caused by wavegiude filters. To evaluate the designed group delay equalizer, various simulated and experimental results are shown here in conjunction with STM-1 signal of co-channel 64-QAM digital radio relay system.

• Journal of the Korean Society for Precision Engineering
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• v.14 no.4
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• pp.88-96
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• 1997

This paper suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteresis nonlinear element which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. A proper Lyapunov function is selected and the Lyapunov direct method is used to prove the asymptotic stability of the suggested control.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1041-1044
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• 2003

In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35${\mu}{\textrm}{m}$ process technology.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.987-993
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• 1996

This report suggests a new non-linear friction compensation for digital control systems. This control adopts a hysteric nonlinear clement which can introduce the phase lead of the control system to compensate the phase delay comes from the inherent time delay of a digital control. The Lyapunov direct method is used to prove the asymtotic stability of the suggested control, and the stability and the effectiveness are verified analytically and experimentally on a single axis servo driving system.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.21-29
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• 2002

This paper describes a high resolution DLL(Delay Locked Loop) using all digital circuits. The proposed architecture is based on the three stage of coarse, fine and ultra fine phase tuning block which has a phase detector, selection block and delay line respectively. The first stage, the ultra fine phase tuning block, is tune to accomplish high resolution using a vernier delay line. The second and third stage, the coarse and fine tuning block, are tuning the phase margin of Unit Delay using the delay line and are similar to each other. It was simulated in 0.35um CMOS technology under 3.3V supply using HSPICE simulator. The simulation result shows the phase resolution can be down to lops with the operating range of 250MHz to 800MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10A
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• pp.1590-1597
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• 2000

This paper describes a CMOS data recovery circuit using oversampling technique. Digital oversampling is done using a delay locked loop circuit locked to multiple clock periods. The delay locked loop circuit generates the vernier delay resolution less than the gate delay of the delay chain. The transition and non-transition counting algorithm for 4x oversampling was implemented for data recovery and verified through FPGA. The chip has been fabricated with 0.6um CMOS technology and measured results are presented.