• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• Journal of Power Electronics
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• 제11권2호
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• pp.156-162
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• 2011

The control loop time delay caused by sampling, the zero-order-holder effect and calculations is inevitable in the digital control of dc-dc switching converters. The time delay will limit the bandwidth of the control loop and therefore degrade the transient performance of digital systems. In this paper, the quantization time delay effects with different time delay values based on a generic second-order system are analyzed. The conclusion that the bandwidth of digital control is reduced by about 20% with a one cycle delay and by 50% with two cycles of delay in comparison with no time delay is obtained. To compensate the time delay and to increase the control loop bandwidth, a duty ratio predictive control scheme based on linear extrapolation is proposed. The compensation effect and a comparison of the load variation transient response characteristics with analogy control, conventional digital control and duty ratio predictive control with different time delay values are performed on a point-of-load Buck converter by simulations and experiments. It is shown that, using the proposed technique, the control loop bandwidth can be increased by 50% for a one cycle delay and 48.2% for two cycles of delay when compared to conventional digital control. Simulations and experimental results prove the validity of the conclusion of the quantization effects of the time delay and the proposed control scheme.

• Journal of information and communication convergence engineering
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• 제8권1호
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• pp.103-106
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• 2010

In this paper, the delay times were evaluated to develop highly reliable time-to-digital converter(TDC) in analog and digital delay element structures. The delay element can be designed by using current source or inverter. In case of using inverter, the number of inverter has to be controlled to adjust the delay time. And in case of using current source, the current for charging and discharging is controlled. When the current source is used the delay time of the delay element is not sensitive with varying the channel width of CMOS. However, when the inverter is used the delay time is directly related to the channel width of CMOS. Therefore to obtain good reliability in TDC circuit the delay element using current source is more stable compared to inverter in the viewpoint of the variation of fabrication process.

• 감성과학
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• 제11권2호
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• pp.227-234
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• 2008

시각과 청각으로 표현된 디지털 콘텐츠가 감각표현을 확장하려는 연구가 활발하다. 최근에는 촉각 표현이 가능한 다양한 촉각 표현 시스템이 개발하여 촉감을 표현하는 디지털 콘텐츠 개발하고 있다. 하드웨어에 의한 촉감각 표현시 다른 감각과의 동기화가 중요한 표현 요소로 대두되고 있다. 본 연구는 햅틱(haptic)표현이 다른 감각에 비해 표현 지연 발생할 경우 실감도에 미치는 영향에 관한 것이다. 시각 및 햅틱 지연 시간을 0.5, 1.0, 2.0, 4.0(초)로 설정하여 각 지연에 대한 실감도 평가를 실시하여 선형 회귀 분석하였다. 촉각 지연 보다 시각 지연에서 실감도와 상관성을 보였으며 지연 시간이 길어질수록 실감도가 떨어지는 것을 볼 수 있었다. 그러므로 사용자는 촉감 표현에 대한 지연이 시각 지연 보다 관대한 것으로 사료된다.

• Journal of Power Electronics
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• 제12권1호
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• pp.98-103
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• 2012

This paper presents a digital pulse width modulator (DPWM) with a reduced digital modulation delay (a transport delay of the modulator) during the transient response of power converters. During the transient response operation of a power converter, as a result of dynamic variations such as load step-up or step-down, the closed loop controller will continuously adjust the duty cycle in order to regulate the output voltage. The larger the modulation delays, the larger the undesired output voltage deviation from the reference point. The three conventional DPWM techniques exhibit significant leading-edge and/or trailing-edge modulation delays. The DPWM technique proposed in this paper, which results in modulation delay reductions, is discussed, experimentally tested and compared with conventional modulation techniques.

• 한국지능시스템학회논문지
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• 제10권5호
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• pp.423-431
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• 2000

In this paper, the effect of computing time-delay in the real-time digital fuzzy control systems is investigated and the design methodology of a real-time digital fuzzy controller(DFC) to overcome the problems caused by it is presented. We propose the fuzzy feedback controller whose output is delayed with unit sampling period. The analysis and the design problem considering computing time-delay is very easy because the proposed controller is syncronized with the sampling time. The stabilization problem of the digital fuzzy control system is solved by the linear matrix inequality(LMI) theory. Convex optimization techniques are utilized to find the stable feedback gains and a common positive definite matrix P for the designed fuzzy control system Furthermore, we develop a real-time fuzzy control system for backing up a computer-simulated truck-trailer with the consideration of the computing time-delay. By using the proposed method, we design a DFC which guarantees the stability of the real time digital fuzzy control system in the presence of computing time-delay.

• 한국음향학회지
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• 제22권8호
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• pp.680-686
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• 2003

디지털 도파관 모델은 악기의 물리적 모델링에 사용되는 일반적인 방법이다. 디지털 도파관 모델에서 파동의 움직임은 시간 또는 공간을 기준으로 해석 가능하다. 음의 샘플링이 시간을 기준으로 이루어지므로 악기 모델은 시간에 의한 파동의 움직임으로 묘사되는 것이 일반적이다. 본 논문에서는 현에 대한 공간 기준의 디지털 도파관 모델에 악기 몸체 모델을 추가해 악기 음을 합성하였다. 그렇게 함으로써 합성 음의 음질을 향상시키고 악기 모델의 음색 조절 변수들을 효과적으로 처리할 수 있었다. 공간 기준 샘플링에서 현 및 몸체에서 발생하는 미소 지연 오차에 대해 설명하고 FD (Fractional Delay) 필터를 이용해 미소 지연을 처리하는 방법을 보였다. 그리고 지연에 수에 따른 합성음의 변화를 설명하고 그 결과를 시간 기준 디지털 도파관 모델과 비교하였다.

• 한국산업정보학회논문지
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• 제20권1호
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• 전기전자학회논문지
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• 제21권4호
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• pp.416-419
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• 2017

본 논문에서는 고속 DDR3/DDR4 SDRAM을 위한 새로운 디지털 지연고정루프 (delay-locked loop: DLL)를 제안한다. 제안하는 디지털 DLL은 디지털 지연라인의 boundary switching 문제에 의한 jitter 증가 문제를 제거하기 위하여 위상보간 (phase interpolation) 방식의 파인지연라인 (fine delay line)을 채택하였다. 또한, 제안하는 디지털 DLL은 harmonic lock 문제를 제거하기 위하여 새로운 점진직 검색 (gradual search) 알고리즘을 사용한다. 제안하는 디지털 DLL은 1.1V, 38-nm CMOS DRAM 공정으로 설계되었으며, 0.25-2.0 GHz의 주파수 동작 영역을 가진다. 2.0 GHz에서 1.1 ps의 피크-투-피크 (p-p) 지터를 가지며, 약 13 mW의 전력소모를 가진다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.932-934
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• 2006

A relationship between discharge delay time and the aging method were investigated: A-Y (Address electrode - Scan electrode) aging and conventional X-Y(Common electrode - Scan electrode) aging with the variation of sustain voltage beyond self-erasing discharge. Although A-Y aging decreases discharge delay time, it has several drawbacks like non-uniformity of discharge, degradation of luminous efficiency and a color temperature. In a conventional aging condition which is carried out near the mid-margin voltage, discharge delay time is short in low voltage and high frequency condition. As an alternative to conventional voltage aging, high voltage aging is suggested which is carried out at self-erasing sustain voltage region. High voltage aging shows lower discharge delay time and fast aging speed than conventional voltage aging.