• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.347-356
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• 1987

This paper is to propose a new line code suitable for a high speed unipolar pulse transmission system, such as a high speed optical digital transmission system. The original information speed can be converted into the transmission speed $\frac{(m+1)}{m}$ by the speed converter. Then this code, named mBiZ code, is generated by means of an Exclusive NOR between the bit stream inserted a space into every m bits and the bit stream delayed by the time slot allocated a single bit at the output coded sequence. Therefore, a mBiZ code can reduce a redundancy in the line code for transmission and its conversion circuits can be devised easily. The mBiZ code can also suppress undesirable long consecuitive identical digits and make line code balance in the mark and space ratio. Therefore, high frequency and low frequency components in power spectrum of a mBiZ code can be suppessed.

• Proceedings of the KIEE Conference
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• 1990.07a
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• pp.433-436
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• 1990

An optimal Stabilization technique for a bilinear in duction model is introduced. This technique includes to o parts; the one is an stabilization control using Lyap unov Function which has the form of a sum of linear and quadratic function of the state variables, and the other is an optimal control using the performance index which depends on the choice of the elements of the Ly apunov matrices concerning both the state variables and the input variables. Therefore, induction motor is drived with the shorter transient time of the state variables and with the smaller overshoot of the ones, simulation results are obtained from a digital computer. Experimental ones are obtained from implementation of the optimizing controller using 8086 microprocessor kits and analog circuits are compared.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.175-182
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• 2000

(A hybrid-type wireless infrared data communication module was fabricated by using the light emitting andabsorption diodes with the one-chip of integrated digital circuits. The light emitting diode with the peak spectrum of 850 nm was made from compound semiconductor material of AIGaAs and shows high speed signal transmission with the delay time of 60 nsec for the light direction angle of 30". The Si PIN photodiode showsthe good absorption rate for the range of wavelength of 450-1050 nm and convex-type epoxy lens was utilized for the spectrum filtering on the visible-range spectrum below 750 nm, The data transmission speed is 115.2 kbps and the fabricated module satisfies on the IrDA 1.0 SIR standard requirements.)ments.)

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.6
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• pp.539-546
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• 2014

This paper describes an ultra-precision electronic clinometer, which is based on the capacitive-based fluid type, for detection of small inclination angles. The main parts of the clinometer low-noise electronics are two capacitance measurement circuits for converting the capacitances of the capacitors of the clinometer into voltages, and a differential amplifier for obtaining the difference of the capacitances, which is proportional to the input inclination angle. A 16 bit analog to digital (AD) converter is also embedded into the same circuit board, whose output is sent to a PC via RS-232C, for achieving a small noise level down to tens of ${\mu}v$. A compensation method, which is referred to as the delay time method for shortening the stabilization time of the sensor was also discussed. Experimental results have shown the possibility of achieving a measurement resolution of $0.0001^{\circ}$ as well as the quick measurement with the delay time method.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.22 no.2
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• pp.170-178
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• 2012

This paper is concerned with the development of power amplifier and controller for piezoelectric actuator and sensor used in smart structures. Even though a high-voltage power amplifier is provided in the form of an operational amplifier, a very high DC voltage is still necessary as a power supply. In this study, we propose a low-cost design for the power amplifier including the DC power supply. We also need a controller on which a control algorithm will be mounted. In general, a digital signal processing chip is popularly used because of high speed. However, only commercial product is available for smart structure applications. In this paper, a controller consisting of a DSP and electronic circuits suitable for piezoelectric sensor and actuator pair is proposed. To validate the proposed controller with power amplifier, experiment on smart structure was carried out. The experimental results show that the proposed control system can be effectively used for smart structure applications with low cost.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.38-46
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• 2006

A parallel analog Viterbi decoder which decodes PRML signal of DVD has been fabricated into a VLSI chip. The parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. In this paper, the analog parallel Viterbi decoding technology is applied for the PRML signal decoding of DVD. The benefits are low power consumption and less silicon consumption. The designed circuits are analysed and the test results of the fabricated chip are reported.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.195-196
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• 2007

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO, five divide-by-2 circuits and several buffers. The simulation results show that the designed circuit has a phase noise at 10kHz better than -87dBc/Hz throughout the signal band and consumes 10mA from a 1.8V supply.