• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.411-417
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• 2012

A Coarse-Fine Time-to-Digital Converter (TDC) using the single time amplifier is proposed. A vernier delay line is used to overcome process dependency and the 2-stage time amplifier is designed to have high resolution by increasing the gain of the time amplifier. Single time amplifier architecture reduces the silicon area of the TDC and alleviates mismatch effect between time amplifiers. The proposed TDC is implemented in $0.18{\mu}m$ CMOS process with the supply voltage of 1.8 V. The measured results show that the resolution of the TDC is 0.73 ps with 10-bit digital output, although highend process is not applied. The single time amplifier architecture reduces 13% of chip area compared to previous work. By reducing the supply voltage, the linearity of the TDC is enhanced and the resolution is decreased to 1.45 ps.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.605-607
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• 2004

A class D digital audio amplifier with small size, low cost, and high quality is positively necessary in the multimedia era made of home theater system and the digital audio broadcasting (DAB). It is impossible to analyze the stability of the digital audio amplifier, which is based on the PWM signal processing. To solve this problem, the digital audio amplifier is analyzed using variable structure control theory which is one of nonlinear system theories. Moreover, the magnitude and the frequency of ripple signal, which generated by hysteresis in the comparator, is obtained using describing function which is useful to represent the input-output relation of nonlinear system.

• Journal of Institute of Control, Robotics and Systems
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• v.13 no.4
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• pp.385-391
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• 2007

A class D digital audio amplifier with small size, low cost, and high quality is positively necessary in the multimedia era. Since the digital audio amplifier is based on the PWM signal processing, it is improper to analyze the principle of signal generation using linear system theories. In this paper, a class D digital audio amplifier based ADSM (Advanced Delta-Sigma Modulation) is considered. We first model the digital audio amplifier and then explain the operation principle using variable structure control algorithm. Moreover, the ripple signal generated by the hysteresis in the comparator has a significant effect on the system performance. Thus, we present a method to find the magnitude and the frequency of the ripple signal using describing function. Finally, simulations and experiments are provided to show the validity of the proposed methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.9-15
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• 1994

In this paper, the linearized power amplifier using digital adaptive predistorter is implemented in order to restrict spectral spreading and adjacent channel interference. The linearized systems is composed of a DSP56001 processor that executes predistortion in baseband. 90.deg. phase shifter, power splitter/combiner, quadrature modulator/demodulator of 360MHz band, and nonlinear amplifier. A ${\pi}$/4-shift QPSK is used to modulate digital random signals. As the quantized power of baseband signal and the output of amplifier are fed to the predistorter, and predistorting values are calculated using an adaptive algorithm. In the experiment, a peak to sidelobe ratio of the linearized amplifier is improved up to 15dB in comparison with conventional nonlinear amplifier, which means that the distortion of transmitted signal is decreased and adjacent channel interference was reduced.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.110-113
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• 1998

An analysis of the relationship between a linear amplifier chain and an analog-to-digital converter(ADC) in a digital microwave widevand receiver, with respect to sensitivity and dynamic range issues, is presented. The effects of gain, third-order intermodulation products and ADC characteristics on the performance of the receiver are illustrated and design criteria for the linear amplifier chain given a specified ADC are developed. A computer program is used to calculate theretical receiver performance based on gain and third-order intermodulation product selections. Simulated results are also presented and compared with theoretical values.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1847-1853
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• 2014

The PAPR of the input signal is increased due to OFDMA signal in a mobile communication system. High efficiency of a power amplifier, which accounts for power consumption, is a very important key technology. Digital Pre-Distortion techniques were used to improve the linearity of the power amplifier. The Asymmetric Doherty scheme was used to improve the efficiency of the power amplifier. In this paper, we propose a new structure of Asymmetric Doherty. Drive power amplifier part is separated as main path and peak path, and phase shifter is employed to improve power combine characteristics of the Doherty Amplifier. Also, envelope tracking technology for drive gate bais in drive peak amplifier is used to improve efficiency.

• ETRI Journal
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• v.35 no.5
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• pp.819-826
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• 2013

A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulse-code modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-${\mu}m$ CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 ${\mu}W$ from a 1.2-V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.1934-1939
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• 2006

Current digital communication system is selecting very various digital Modulation way. Need linear power amplifier necessarily to reduce interference for contiguity channel maximum in this communication system and at the same time, power amplifier of high efficiency is required. In this paper Compare with result of equilibrium power amplifier that design Doherty power amplifier of way that linearity and efficiency are improved at the same time through simulation optimization techniques and at the same time design through simulation, efficiency 20% linearity showed 10dB that is improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.485-491
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• 2003

In this paper, We designed the multi-stage amplifier having high gain/low noise characteristics for terrestial repeater of direct digital satellite broadcasting system. In the design the amplifier, we optimized the parameters to have the stable operation between gain, noise figure and stability. The first stage of amplifier can be specified low noise impedance matching, 2nd stage to 5th stage show constant gain and stable operation and final stage of amplifier shows high gain impedance matching. As a result of experiment at the frequency of digital satellite terrestial, show 68dB gain under 2,4dB noise figure and 63dB dynamic range in the 11.7GHz-12.7GHz frequency range, it is a good agreement of communication channel amplifier requirements for satellite terrestial repeater.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.149-156
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• 2012

A digital input class-D audio amplifier is presented for digital hearing aid. The class-D audio amplifier is composed of digital and analog circuits. The analog circuit converts a digital input to a analog audio signal (DAC) with noise suppression in the audio band. An interpolated digital delta-sigma modulator is used to convert data types between digital signal processor (DSP) and digital-to-analog converter (DAC). An 16-bit, 25-kbps pulse code modulated (PCM) input is interpolated to 16-bit, 50-kbps by a digital filter. The output signal of interpolation filter is noise-shaped by a third-order digital sigma-delta modulator (SDM). As a result, 1.5-bit, 3.2-Mbps signal is applied to simple digital to analog converter.