• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.3 s.303
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• pp.107-114
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• 2005

Edge enhanced image is needed for processing images for special purpose such as a circuit diagram or a design composed of lines. Error diffusion halftoning, among digital halftoning methods to represent a continuous grayscale image for the binary output device such as printers, facsimiles, LCD televisions and etc. also makes edges of objects blurred. This paper proposes the method to enhance the edge of a binary image for the binary output device as well as a circuit diagram or a design. Based on that the human eyes perceive the local average luminance rather than the pixel's luminance itself, the proposed system uses a local activitymeasure (LAM), which is the difference between a pixel luminance and the average of its $3{\times}3$ neighborhood pixels' luminances weighted according to the spatial positioning. The system also usesinformation of edge enhancement(IEE), which is computed from the LAM multiplied by the average luminance. The IEE is added to the quantizer's input pixel and feeds into the halftoning quantizer. The quantizer produces the halftone image having the enhanced edge. The simulation results show that the proposed method produces more fine halftoning images than conventional methods due to the enhanced edges. Also the performance of the proposed method is compared with that of the conventional method by measuring the edge correlation and the local average accordance over a range of viewing distances.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.10
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• pp.33-46
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• 2015

In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.205-215
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• 2013

In digital imaging system, Bayer pattern is widely used and the observed image is degraded by optical blur during image acquisition process. Generally, demosaicing and deblurring process are separately performed in order to convert a blurred Bayer image to a high resolution color image. However, the demosaicing process often generates visible artifacts such as zipper effect and Moire artifacts when performing interpolation across edge direction in Bayer pattern image. These artifacts are emphasized by the deblurring process. In order to solve this problem, this paper proposes a deblurring algorithm combined with edge directional color demosaicing method. The proposed method is consisted of interpolation step and region classification step. Interpolation and deblurring are simultaneously performed according to horizontal and vertical directions, respectively during the interpolation step. In the region classification step, characteristics of local regions are determined at each pixel position and the directionally obtained values are region adaptively fused. Also, the proposed method uses blur model based on wave optics and deblurring filter is calculated by using estimated characteristics of local regions. The simulation results show that the proposed deblurring algorithm prevents the boosting of artifacts and outperforms conventional approaches in both objective and subjective terms.

• Journal of Korea Game Society
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• v.9 no.5
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• pp.25-41
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• 2009

The objective of this study is to develop an analytic framework to code systematically the gamer's behaviour in MMO(Massively Multi-player Online) gameplay experience, to explore their gameplay as a problem solving procedure empirically. Previous studies about model human processor, content based protocol, and procedure based protocol are reviewed in order to build the outline of the analytic framework related to MMO gameplay. The specific gameplay actions and contents were derived by using concurrent protocol analysis method through the empirical experiment executed in MMORPG gameplay. Consequently, gameplay are divided into six actions : kinematics, perception, function, representation, simulation, and rule (heuristics, following, and transcedence). The analytic framework suitable for MMO gameplay was built. As a result of this study, we found three rule spaces in the problem solving domain of gameplay that are an heuristics, a following of the rule, and a transcendence of the rule. 'Heuristics' denotes the rule action that discovers the rule of game through trial-and-error. 'Following' indicates the rule action that follows the rule of game embedded in game by game designers. 'Transcendence' presents the rule action that transcends that. The new discovered rule spaces where 'Following' and 'Transcendence' actions occur and the gameplay pattern in them is provided with the key basis to determine the level design elements of MMO game, such as terrain feature, monster attribute, item, and skill et cetera. Therefore, this study is concludes with key implications to support game design to improve the quality of MMO game product.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.184-193
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• 2012

In this paper, a 5-bit 2-GS/s 2-way time interleaved pipeline ADC for high-speed serial link receiver is demonstrated. Implemented as a current-mode amplifier, the stage ADC simultaneously processes the tracking and residue amplification to achieve higher sampling rate. In addition, each stage incorporates a built-in 1-tap FIR equalizer, reducing inter-symbol-interference (ISI）without an extra digital post-processing. The ADC is designed in a 110nm CMOS technology. It comsumes 91mW from a 1.2-V supply. The area excluding the memory block is $0.58{\times}0.42mm^2$. Simulation results show that when equalizer is enabled, the ADC achieves SNDR of 25.2dB and ENOB of 3.9bits at 2.0GS/s sample rate for a Nyquist input signal. When the equalizer is disengaged, SNDR is 26.0dB for 20MHz-1.0GHz input signal, and the ENOB of 4.0bits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.9 s.351
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• pp.149-157
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• 2006

Turbo code, a kind of error correction coding technique, has been used in the field of digital mobile communication system. As the number of iterations increases, it can achieves remarkable BER performance over AWGN channel environment. However, if the number of iterations is increased in the several channel environments, any further iteration results in very little improvement, and requires much delay and computation in proportion to the number of iterations. To solve this problems, it is necessary to device an efficient criterion to stop the iteration process and prevent unnecessary delay and computation. In this paper, it proposes an efficient and simple criterion for stopping the iteration process in turbo decoding. By using variance values of LLR in turbo decoder, the proposed algerian can largely reduce the average number of iterations without BER performance degradation in all SNR regions. As a result of simulation, the average number of iterations in the upper SNR region is reduced by about $34.66%{\sim}41.33%$ compared to method using variance values of extrinsic information. the average number of iterations in the lower SNR region is reduced by about $13.93%{\sim}14.45%$ compared to CE algorithm and about $13.23%{\sim}14.26%$ compared to SDR algorithm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.4
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• pp.7-13
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• 2012

The performance of blind equalization algorithm ISCA was compared with MSCA that is used for the minimization of the inter symbol interference which occurs in the time dispersive communication channel for digital transmission. Because of the non-linearities of a magnitude and phase transfer characteristics of a communication channel, the transmitting signal will be received that band limited and time dispersived. Therefore the distortion was compensated by using the self adaptive equalizer at the receiving side, then passing through the detector for the decision of "1" or "0". At this time the Constellation Dependent Constant is played an important role in the adaptive equalizer used on the receiver. In order to calculation of this constant, the ISCA and MSCA was used the second order statistics. The ISCA and MSCA which are possible to compensation of mensioned transfer function simulataneously, are improved the performance of original SCA algorithm and then was compared the performance by computer simulation. For this, the recovered constellation, residual isi and MSE was used, and a result of performance comparison, the ISCA algorithm has better than the MSCA in every performance index. But on the steady state of equalizer, the variation of performance due to the CME terms in the MSCA equalization algorithm was less than the ISCA, so MSCA has better stability.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Proceedings of the Korean Society of Crop Science Conference
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• 2017.06a
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• pp.315-315
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• 2017

In Japan, more than 80 % of soybean growing area is converted fields and excess water is one of the major problems in soybean production. For example, recent study (Yoshifuji et al., 2016) suggested that in the fields of shallow groundwater level (GWL) (< 1m depth), rising GWL even in a short period (e.g. 1 day) causes inhibition of soybean growth. Thus it becomes more and more important to predict GWL and soil moisture in detail. In addition to conventional surface drainage and underdrain, FOEAS (Farm Oriented Enhancing Aquatic System), which is expected to control GWL in fields adequately, has been developed recently. In this study we attempted to predict GWL and soil moisture condition at the converted field with FOEAS in Biwa lake reclamation area, Shiga prefecture, near the center of the main island of Japan. Two dimensional HYDRUS model (Simuinek et al., 1999) based on common Richards' equation, was used for the calculation of soil water movement. The calculation domain was considered to be 10 and 5 meter in horizontal and vertical direction, respectively, with two layers, i.e. 20cm-thick of plowed layer and underlying subsoil layer. The center of main underdrain (10 cm in diameter) was assumed to be 5 meter from the both ends of the domain and 10-60cm depth from the surface in accordance with the field experiment. The hydraulic parameters of the soil was estimated with the digital soil map in "Soil information web viewer" and Agricultural soil-profile physical properties database, Japan (SolphyJ) (Kato and Nishimura, 2016). Hourly rainfall depth and daily potential evapo-transpiration rate data were given as the upper boundary condition (B.C.). For the bottom B.C., constant upward flux, which meant the inflow flux to the field from outside, was given. Seepage face condition was employed for the surrounding of the underdrain. Initial condition was employed as GWL=60cm. Then we compared the simulated and observed results of volumetric water content at depth of 15cm and GWL. While the model described the variation of GWL well, it tended to overestimate the soil moisture through the growing period. Judging from the field condition, and observed data of soil moisture and GWL, consideration of soil structure (e.g. cracks and clods) in determination of soil hydraulic parameters at the plowed layer may improve the simulation results of soil moisture.