• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.240-243
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• 2001

This paper presents the digital controller using variable gain for single-phase power factor correction (PFC) converter. Generally, the gain of inner current control loop in single-stage PFC converter has a constant magnitude. This is why input current is distorted under low input voltage. In particular, a digital controller has more time delay than an analog controller which degrades characteristics of control loop. So, it causes the problem that the gain of current control loop isn't increased enough. In addition, the oscillation happens in the peak value of the input voltage open loop PFC system gain changes according to ac input voltage. These aspects make the design of the digital PFC controller difficult. In this paper, the improved digital control method for single-phase power factor converter is presented. The variable gain according to input voltage and input current help to improve current shape. The 800W converter is manufactured to verify the proposed control method.

• KEPCO Journal on Electric Power and Energy
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• v.6 no.4
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• pp.405-411
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• 2020

In this paper, we designed the COS MEMS system for sensing the falling detection and explosive noise of fuse link in COS (Cut Out Switch) installing on the power distribution. This system analyzed the failure characteristics and an instantaneous breakdown of power distribution. Therefore, our system strengths the industrial competence and guaranties the stable power supply. In this paper, we applied BLE (Bluetooth Low Energy) technology which is suitable protocol for low data rate, low power consumption and low-cost sensor applications. We experimented with LSM6DSOX which is system-in-module featuring 3 axis digital accelerometer and gyroscope boosting in high-performance mode and enabling always-on low-power features for an optimal motion for the COS fuse holder. Also, we used the MP34DT05-A for gathering an ultra-compact, low power, omnidirectional, digital MEMS microphone built with a capacitive sensing element and an IC interface. The proposed COS MEMS system is developed based on nRF52 SoC (System on Chip), and contained a 3-axis digital accelerometer, a digital microphone, and a SD card. In this paper of experiment steps, we analyzed the performance of COS MEMS system with gathering the accelerometer raw data and the PDM (Pulse Data Modulation) data of MEMS microphone for broadcasting the failure of COS status.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• Proceedings of the KIPE Conference
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• 2004.07a
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• pp.194-194
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• 2004

This paper presents Single Phase SRM for the vacuum cleaner. The advantage of SRM is long life time, high suction power.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.2
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• pp.31-37
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• 2001

Digital servo implementation in optical servo chip has been spotlighted since it is easy to integrate with other blocks and it has less sensitive characteristics change in terms of temperature variation and better flexibility to the system variation like pick-up. Therefore, Optical disc players adopted digital servo are increasing in market. However, one drawback of digital signal processor embedded digital servo is power consumption that is one of the most important factors of portable optical disc player system. For that reason, this paper introduces new architecture to reduce power consumption of digital servo by means of reducing DSP load but increasing minimum hardware size. The main idea of reducing power consumption of digital servo greatly is utilizing CDP characteristics as most operations are done and used up most operating steps of DSP at the initial time, but most power consumption is occurred in play mode. Therefore, if operating steps for digital filtering in play mode could be reduced greatly, power consumption of overall system can be reduced greatly. This paper shows an example that low power digital servo architecture whose current is reduced almost 83%, compare to that of digital servo which is not applied by the low power architecture introduced in this paper.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.10-17
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• 2010

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using $0.13-{\mu}m$ CMOS process under 1.2V supply.

• KIEE International Transactions on Power Engineering
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• v.3A no.2
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• pp.93-99
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• 2003

This paper deals with the development and testing of a large-scale, realtime digital power system simulator for the Korean Electric Power Corporation. The KEPS Simulation Center is located at KEPCO's research center (KEPRI) in Taejon, South Korea and has been operated since September 2001. The KEPS Simulation Center includes a wide range of off line power system simulation and analysis tools, as well as an advanced realtime digital simulator for the study of large scale AC and DC system performance. Because the application scope of the KEPS realtime simulator is broad and because the network models being considered are significantly larger and more complex than in traditional realtime simulator applications, many developments and tests have been required during the course of the project. In this paper, the authors describe some of these developments and present results from various benchmark tests that have been performed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.9
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• pp.1728-1734
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• 2009

This paper proposes a new power conditioning system for the fuel cell power generation, which consists of a ZVS DC-DC converter and 3-phase inverter. The ZVS DC-DC converter with a digital controller boosts the fuel cell voltage of 26-50V up to 400V, and the grid-tie inverter controls the active power delivered to the grid. The operation of proposed power conditioning system was verified through simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was verified through experimental works with a laboratory prototype, which was built with 1.2kW PEM fuel-cell stack, 1kW DC-DC converter, and 3kW PWM inverter. The proposed system can be utilized to commercialize an interconnection system for the fuel-cell power generation.

• KEPCO Journal on Electric Power and Energy
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• v.7 no.2
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• pp.285-293
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• 2021

The construction of underground structures such as power supply lines, communication lines, utility tunnels has significantly increased worldwide for improving urban aesthetics ensuring citizen safety, and efficient use of underground space. Those underground structures are usually constructed along with vertical cylindrical shafts to facilitate their construction and maintenance. When constructing a vertical shaft through the open-cut method, the walls are mostly designed to be flexible, allowing a certain level of displacement. The earth pressure applied to the flexible walls acts as an external force and its accurate estimation is essential for reasonable and economical structure design. The earth pressure applied to the flexible wall is closely interrelated to the displacement of the surrounding ground. This study simulated stepwise excavation for constructing a cylindrical vertical shaft through a centrifugal model experiment. One quadrant of the axisymmetric vertical shaft and the ground were modeled, and ground excavation was simulated by shrinking the vertical shaft. The deformation occurring on the entire ground during the excavation was continuously evaluated through digital image analysis. The digital image analysis evaluated complex ground deformation which varied with wall displacement, distance from the wall, and ground depth. When the ground deformation data accumulate through the method used in this study, they can be used for developing shaft wall models in future for analyzing the earth pressure acting on them.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.