• Journal of Advanced Marine Engineering and Technology
• /
• v.30 no.3
• /
• pp.444-448
• /
• 2006

In this paper, a frequency synthesizer for X-band FMCW radars is proposed. Some X-band FMCW radars have been used as a level sensor for tanker ship and the resolution of the level sensor may be mainly depend on linearity of frequency sweep. For a linear frequency sweep. the proposed synthesizer employs a phase-locked loop using prescalars and a high speed digital PLL chip. The measured results show that the linear frequency sweep range is from 10 GHz to 11 GHz and the output power of the synthesizer is minium 7 dBm. and the phase noise is about -80 dBc/Hz at 100 KHz offset from 11 GHz.

• Proceedings of the Korean Society of Marine Engineers Conference
• /
• 2006.06a
• /
• pp.109-110
• /
• 2006

The performance of a digital baseband signal processing and data transmission rate depends on the modulation technique. In this paper, We implemented DSP communication system for Underwater acoustic communication using by adaptive BPSK modem technique. In order to implement adaptive modem, we suggested SNR detection block. SNR detection block has the reference SNR value that selects between window filter path and matched filter path. In this paper, suggested system is based on software interface and all Hardware(PLL, modem filter, equalizer etc) is implemented by software, exclusive of DSP, A/D, D/A converter, SDRAM and Flash memory.

• Proceedings of the KIEE Conference
• /
• 1990.07a
• /
• pp.332-335
• /
• 1990

A digital phase-locked loop speed control system of a self-controlled permanent magnet synchronous mortar fed by a voltage source inverter is presented. This paper discribes the hardware and software design of the system. Variable speed control system for self-controlled permanent magnet synchronous motor is proposed. Simulation results demonstrate the validity of proposed methods. This proposed control technique is implemented by using a microprocessor-based system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.3
• /
• pp.622-628
• /
• 1996

This paper describes a new serial interface system which uses conventional 75 ohm coaxial cable. Typically parallel 25 pin cable and connectors are used to transfer and receive the data between digital systems such as HDVCR, D3 VTR and HDTV Receiver. The coaxial cable is more desirable for consumer product applications and also for studio applications where long signal paths and switching are required. This serial data transfer technique is thoroughly tested and utilied in the data transmission/reception between systems more than 200 feet apart. It is also cost effective because it does not require RF PLL, SCRAMBLING, and NRZI hardware.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.247-255
• /
• 2011

This paper describes a CMOS outphasing transmitter using two wideband phase modulators. The proposed architecture can simplify the overall outphasing transmitter architecture using two-point phase modulation in phase-locked loop, which eliminates the necessity digital-to-analog converters, filters, and mixers. This architecture is verified with a WCDMA signal at 1.65 GHz. The prototype is fabricated in standard 130 nm CMOS technology. The measurement results satisfied the spectrum mask and 4.9% EVM performance.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.77-80
• /
• 2003

We design the local oscillator system of the 100 GHz band radio receiving system for a cosmic radio observation. We use the YIG oscillator with digital driver which is the main oscillator. This oscillator has a good frequency and phase stability at some temperature variation, and the easy computer aided control characteristics. This total system designed to two subsystem, first is the oscillator system include YIG oscillator, tripler, harmonic mixer and triplexer etc., second is the PLL system to supply the precise and stable local oscillator frequency to mixer. The proposed local oscillator system in this paper can be use a single or multi pixel receiver because this system can be lock the local oscillator frequency automatically using PC.

• Proceedings of the KIPE Conference
• /
• 2005.07a
• /
• pp.54-56
• /
• 2005

The paper proposes the solar photovoltaic power generation system method for photovoltaic system to solve the power shortage due the sudden power demand. So that supplied electric power to system at appearance during surplus electric power minute and unit moment link driving with common use system is available, digital PLL circuit system voltage through composition and phase of solar photovoltatic power generation system to do synchronization do. Feed forward controller was applied to get fast current response Solar cell that is changed by solar radiation always kept the maximum output when it used Step up chopper. The dynamic character had checked through simulation used Matlab Sumulink and confirmed through an experiment.

• Proceedings of the KIPE Conference
• /
• 2007.07a
• /
• pp.441-443
• /
• 2007

In this paper, The authors design the current controller which independently control the d, q axis current transformed by the synchronously rotating d, q axis and a Space Vector Pulse Width Modulation(SVPWM) to steadily control the output DC-Link voltage against the variable load of the three phase PWM converter. Also, This study improves the high power factor, stability, and rapid response by the phase angle control using the digital Phase Locked Loop(PLL).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.272-281
• /
• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.8A
• /
• pp.785-793
• /
• 2007

This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.