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Design of Digital Signal Processor for Ethernet Receiver Using TP Cable  

Hong, Ju-Hyung (삼성전자 System LSI 사업부)
SunWoo, Myung-Hoon (아주대학교 전자공학부)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.32, no.8A, 2007 , pp. 785-793 More about this Journal
Abstract
This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.
Keywords
100Base-TX Ethernet; BLW compensator; Adaptive equalizer; Timing recovery; PGA;
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  • Reference
1 Intel corporation, LXT972A data sheet, Available : http://www.intel.com
2 Jae Hyung Baek, Ju hyung Hong, and Myung H. Sunwoo, 'Novel Digital Signal Processing Unit for Ethernet Receiver,' in proc. IEEE Int. Symp. Circuits Syst. (ISCAS'2005), May 2005, pp. 4477-4480
3 Douglas L. Jones, 'Learning characteristics of transpose-form LMS adaptive filters,' IEEE Trans. Circuits Syst. II, vol 39, pp. 745-749, Oct. 1992   DOI
4 Mysticom corporation, MystiPHY110 product brief, Available : http://www. mysticom.com
5 I. Greiss and E. Lida, 'Digital base-band Receiver,' United States, Patent US 2002/0021767 A1, Jun. 7, 2001
6 IEEE, Part3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications, IEEE Std. 802.3, 2002
7 Jim Rivernider, 'Return loss and data transmission,' Available : http://www.quabbin. com
8 S. Huss, M. Mullen, and C.T. Gray, 'A DSP based 10BaseT/100BaseTX Ethernet transceiver in a 1.8 V, 0.18 $\mu$m CMOS technology,' in proc. IEEE Custom Integrated Circuits Conf., 2001, pp. 135-138
9 Mel Buzes, ' Method and apparatus for reducing baseline wander,' United States, Patent 6,140,857, Mar. 29, 1999
10 Leon Chia-Liang Lin and Gerchih Chou, 'Automatic gain control for communication receivers,' United States, Patent US 2003/0142659 A1. Jun. 25, 2002
11 Jyh-Ting Lai, 'Receiver for baseline wandering compensation,' United States, Patent US 2003/0206604 A1, Jul. 12, 2002
12 ANSI, Fiber distributed data interface (FDDI) - token ring twisted pair physical layer medium dependent (TP-PMD), ANSI x3.263-1995, Sep. 1995
13 Broadcom corporation, BMC5208 data sheet, Available : http://www.broadcom. com
14 K. H. Mueller and M. Muller, 'Timing recovery in digital synchronous data recievers,' IEEE Trans. Commun., vol. COM-24, pp.516-531, May 1976
15 J. H. Lee, W. H. Park, J. H. hong, M. H. Sunwoo and K. H. Kim, 'A high-speed blind DFE equalizer using an error feedback filter for QAM modems,' in proc. IEEE Int. Symp. Circuits Syst. (ISCAS' 2003), May 2003, pp.464-467
16 Sren A. Raghavan, ' Digital baseline wander correction sircuit,' United States, Patent US 6,415,003 B1, Sep. 11, 1998