• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.3
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• pp.45-53
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• 2019

Moving image sharing technology has developed various servers and programs for personal broadcasting. In this paper, we propose the method of transmitting the multiple moving image, including the output channel of external streaming server. It also implements and tests multiple real-time broadcast channel automatic transmission systems that assign multiple output channels to automatic output channels. As a result of the experiment, it is easy to allocate moving image to broadcast channels that are output through the external streaming server's output channels regardless of the size of the streaming server, enabling the management of efficient output channels at the time of transmission of multiple moving image. The moving image can be provided through streaming method regardless of the type of moving image from the moving image provider terminal, and the moving image transmission can be controlled in various ways, including adding and changing channels for which the moving image is sent, and sending delayed to the moving image.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.4
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• pp.243-250
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• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1154-1162
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• 2016

This paper proposes a fast-transient digital LDO(Low dropout) regulator with binary-weighted current control technique. Conventional digital LDO takes a long time to stabilize the output voltage, because it controls the amount of current step by step, thus ringing problem is generated. Binary-weighted current control technique rapidly stabilizes output voltage by removing the ringing problem. When output voltage reliably reaches the target voltage, It added the FRZ mode(Freeze) to stop the operation of digital LDO. The proposed fast response digital LDO is used with a slow response DC-DC converter in the system which rapidly changes output voltage. The proposed digital controller circuit area was reduced by 56% compared to conventional bidirectional shift register, and the ripple voltage was reduced by 87%. A chip was implemented with a $0.18{\mu}F$ CMOS process. The settling time is $3.1{\mu}F$ and the voltage ripple is 6.2mV when $1{\mu}F$ output capacitor is used.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.9
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• pp.685-690
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• 1987

Adaptive design of IIR digiral filters using equation error method has been studied. In this paper, a design technique of IIR digital filters using output error method with adaptive compensator is presented. In computer simulation results, it is shown that flat response characteristic in pass-band, below-40[dB] attenuation characteristic in stop-band, sharf cut-off characteristic in transition-band, and phase characteristic is linearin pass-band.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.64.5-64
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• 2002

This paper concerns a new digital redesign (DR) technique for an observer-based output-feedback control (OBOFC) system. The term DR involves converting an analog controller into an equivalent digital one in the sense of state-matching. The considered DR problem is formulated as convex minimization problems of the norm distances between linear operators to be matched. The stability condition is easily embedded and the separation principle on the DR of the OBOFC is explicitly shown. A numerical example is included for visualizing the feasibility of the proposed technique.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.232-237
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• 1991

Digital Variable Structure Controller(DVSC) is proposed to control variable speed recirculating pump for hot-water heating control system. In this study, nonlinear sliding line is used beyond output error boundary layer and PID sliding line is used within the layer. For long dead time compensation, constraint is added to Smith predictor algorithm. Steady state error is eliminated by using the proposed sliding line in spite of heating load change. By decreasing sampling time, good sliding motion is yielded but system output noise bv flow dynamics is amplified.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.522-527
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• 1987

This paper describes the hardware of analog-to-digital converter to process the rate output of analog servo loop for the gyro rebalance of INS. The analog-to-digital converter is designed by voltage-to-frequency method which is generally used in INS, and this scheme fits well into the strapdown INS that requires the wide dynamic range and linearity. The output of the designed voltage to frequency converter is tested by computer through the counter and all the factors which affect the performance are considered.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1227-1229
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• 2000

The output voltage of UPS must not vary according to the load variation But the output voltage varies due to the load variation when a PI voltage regulator is used which has inherently a static state error. This paper presents a static-error-free digital PID voltage regulator for an UPS inverter to overcome additionally the voltage unbalance problem in three Phase system as well as the above problem.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.110-114
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• 1987

It is known that digital circuits may produce correct output signals even when some faults are present in them. A reliability measure, known as signal reliability, is the probability that the circuit output is correct. In this paper, the reliability measure is analyzed first and a new procedure for evaluation of the signal reliability is presented. This procedure simplifies signal reliability calculations and can easily be mechanized.