• Title/Summary/Keyword: Digital Logic Method

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Development of Rule-Based Knowledge Representation Supporting Tool for Design Digital Moister System (설계 디지털 마이스터 시스템 구축을 위한 규칙 기반 지식 표현 지원 도구 개발)

  • Nam S.H.;Kang H.W.;Lee W.;Suh H.W.;Choi H.J.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2006.05a
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    • pp.633-634
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    • 2006
  • Recently we started a development of the digital meister expert system for the product design supporting in manufacturing industry. Knowledge representation is of major importance in digital moister expert system. This rule-based expert system-knowledges are designed for a certain type of knowledge representation such as rules or logic. The way in which a rule-based expert system represents knowledge affects the development, efficiency, speed, and maintenance. Eventually, this digital moister system is used to the engineer in manufacturing industry for the process control, production management and system management. In this paper, we propose the digital moister system knowledge representation method for product design supporting in manufacturing industry and we present introduction and contents of rule-based knowledge representation supporting tool.

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Development of the Automation System for a fish Pump(I) -Adjustable Speed Control of a Fish Pump Using a Simplified PWM Inverter- (피쉬펌프의 자동화 시스템 개발(I) -간이화 PWM 인버터를 이용한 피쉬펌프의 가변속 제어-)

  • 정석권
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.35 no.3
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    • pp.328-334
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    • 1999
  • A fish pump makes very important roles in an automation system of an aquaculture farm, thus it has been used widely in order to transfer fishes from one place to the other place automatically. In spite of its significant roles, the efforts for developing performance and promoting efficiency of the fish pump are not sufficient yet. In this paper, a method which makes the fish pump automation system is suggested. Automation of the fish pump can be accomplished by using variable voltage and variable frequency inverter system including induction motors. Especially, very simple logic to generate Pulse width Modulation(PWM) wave to control induction motor efficiently and three steps speed control method to regulate liquid quantity of the fish pump simply are suggested. Owing to the simplifies speed control and PWM wave generation technique, a cheaper microprocessor, 80C196KC, than a digital signal Processor(DSP) can be used to operate control algorithm in induction motor systems for real time control Also, a new idea of remote control for the simplifies novel inverter system by Programmable logic Controller(PLC) without special output unit, digital to analog converter(D/A), is suggested in this paper. Consequently the function of reliability, availability and serviceability of the fish pump system are developed. It will be expected to contribute expanding of application of the fish pump in aquaculture farms because the system can reduce energy consumption and some difficulties according to manual operation prominently.

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Design and Implementation of Embedded Contactless (Type-B) Protocol Module for RFID (RFID를 위한 내장형 비접촉(Type-B) 프로토콜 지원 모듈 설계 및 구현)

  • Jeon, Yong-Sung;Park, Ji-Mann;Ju, Hong-Il;Jun, Sung-Ik
    • The KIPS Transactions:PartA
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    • v.10A no.3
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    • pp.255-260
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    • 2003
  • In recent, as a typical example of RFID, the contactless IC card is widely used in traffic, access control system and so forth. And its use becomes a general tendency more and more because of the development of RF technology and improvement of requirement for user convenience. This paper describes the hardware module to process embedded contactless protocol for implementation contactless IC card. And the hardware module consists of analog circuits and specific digital logic circuits. This paper also describes more effective design method of contactless IC card, which method separates into analog circuit parts, digital logic circuit part, and software parts according to the role of the design parts.

Digital Control for Takagi-Sugeno Fuzzy System with Multirate Sampling

  • Kim, Do Wan;Joo, Young Hoon;Park, Jin Bae
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.4 no.2
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    • pp.199-204
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    • 2004
  • In this paper, a new dual-rate digital control technique for the Takagi-Sugeno (T-S) fuzzy system is suggested. The proposed method takes account of the stabilizablity of the discrete-time T-S fuzzy system at the fast-rate sampling points. Our main idea is to utilize the lifted control input. The proposed approach is to obtain the dual-rate discrete-time T-S fuzzy system by discretizing the overall dynamics of the T-S fuzzy system with the lifted control, and then to derive the sufficient conditions for the stabilization in the sense of the Lyapunov asymptotic stability for this system. An example is provided for showing the feasibility of the proposed discretization method.

A study on low power and design-for-testability technique of digital IC (저전력 소모와 테스트 용이성을 고려한 회로 설계)

  • 이종원;손윤식;정정화;임인칠
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.875-878
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    • 1998
  • In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

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Design of an Asynchronous eFuse One-Time Programmable Memory IP of 1 Kilo Bits Based on a Logic Process (Logic 공정 기반의 비동기식 1Kb eFuse OTP 메모리 IP 설계)

  • Lee, Jae-Hyung;Kang, Min-Cheol;Jin, Liyan;Jang, Ji-Hye;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.7
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    • pp.1371-1378
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    • 2009
  • We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

Implementation of Process System and Intelligent Monitoring Environment using Neural Network

  • Kim, Young-Tak;Kim, Gwan-Hyung;Kim, Soo-Jung;Lee, Sang-Bae
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.4 no.1
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    • pp.56-62
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    • 2004
  • This research attempts to suggest a detecting method for cutting position of an object using the neural network, which is one of intellectual methods, and the digital image processing method. The extraction method of object information using the image data obtained from the CCD camera as a replacement of traditional analog sensor thanks to the development of digital image processing. Accordingly, this research determines the threshold value in binary-coding of an input image with the help of image processing method and the neural network for the real-time gray-leveled input image in substitution for lighting; as a result, a specific position is detected from the processed binary-coded image and an actual system designed is suggested as an example.

A Study on the Performance of the Watermarking with Wavelet Transform

  • Kang, Hwan-Il;Park, Hwan-soo
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.1 no.1
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    • pp.24-28
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    • 2001
  • Wavelet transforms are used for implementing digital watermarking methods in the frequency domain. In this paper, we construct the digital watermarking using various wavelet transforms such as the Daubechies transform, Coiflets transform, Symlets transform and the biorthogonal transform, and we compare each digital watermarking method with the others. We investigate the preservation of the watermark after the data compression attack based on the discrete on the discrete cosine transform. We show that the biorthogonal wavelet, denoted by bior3.5, has the best performance among the wavelet types we selected in an experiment.

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Design of Digital Circuit Structure Based on Evolutionary Algorithm Method

  • Chong, K.H.;Aris, I.B.;Bashi, S.M.;Koh, S.P.
    • Journal of Electrical Engineering and Technology
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    • v.3 no.1
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    • pp.43-51
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    • 2008
  • Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.

Efficient FPGA Logic Design for Rotatory Vibration Data Acquisition (회전체 진동 데이터 획득을 위한 효율적인 FPGA 로직 설계)

  • Lee, Jung-Sik;Ryu, Deung-Ryeol
    • 전자공학회논문지 IE
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    • v.47 no.4
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    • pp.18-27
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    • 2010
  • This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.