• Journal of Power Electronics
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• v.10 no.4
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• pp.365-373
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• 2010

This paper proposes a hybrid single carrier sinusoidal modulation suitable for multiphase multilevel inverters. Multiphase multilevel inverters are controlled by hybrid modulation to provide multiphase variable voltage and a variable frequency supply. The proposed modulation combines the benefits of fundamental frequency modulation and single carrier sinusoidal modulation (SC-SPWM) strategies. The main characteristics of hybrid modulation are a reduction in switching losses and improved harmonic performance. The proposed algorithm can be applied to cascaded multilevel inverter topologies. It has low computational complexity and it is suitable for hardware implementations. SC-SPWM and its base modulation design are implemented on a TMS320F2407 digital signal processor (DSP). A Complex Programmable Logic Device realizes the hybrid PWM algorithm and it is integrated with a DSP processor for hybrid SC-SPWM generation. The feasibility of this hybrid modulation is verified by spectral analysis, power loss analysis, simulation and experimental results.

• Proceedings of the KAIS Fall Conference
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• 2007.11a
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• pp.78-80
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• 2007

According to the development of VLSI integration technology and getting bigger the circuit size, it is a significant problem to verify systemized circuit. The faster and more accurate verification has very significant meaning in the field of electronic industry because it can yield the product comparably faster and reduce the trial and errors. In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.3
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• pp.101-109
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• 2019

In addition to enabling access, database accounts play a protective role by defending the database from external attacks. However, because only a single account is used in the database, the account becomes the subject of vulnerability attacks. This common practice is due to the lack of database support, large numbers of users, and row-based database permissions. Therefore if the logic of the application is wrong or vulnerable, there is a risk of exposing the entire database. In this paper, we propose a Least-Privilege Account Separation Model (LPASM) that serves as an information guardian to protect the database from attacks. We separate database accounts depending on the role of application services. This model can protect the database from malicious attacks and prevent damage caused by privilege escalation by an attacker. We classify the account control policies into four categories and propose detailed roles and operating plans for each account.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• Journal of Engineering Education Research
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• v.6 no.2
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• pp.5-14
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• 2003

In this paper, we developed an efficient virtual experiment kit with creative and interactive multimedia contents, which can be used to enhance the quality of education in the area of digital logic circuits. Since our virtual experiment kit is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. Also, our web-based virtual experiment kit is designed to enhance the efficiency of both the learners and the educators. The learners will be able to achieve high learning standard and the educators save time and labor. The virtual experiment is performed according to the following procedure: (1) Circuit Composition on the Bread Board (2) Applying Input Voltage (3) Output Measurements (4) Checkout of Experiment Results. Furthermore, the circuit composition on the bread board and its corresponding online schematic diagram are displayed together on the virtual experiment kit for the learner's convenience. Finally, we have obtained several affirmative effects such as reducing the total experimental hours and the damage rate for experimental equipments and increasing learning efficiencies as well as faculty productivity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.1-6
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• 2006

This paper proposes substrate-bias voltage generator to reduce leakage power consumption of digital logic circuits operating at supply voltage of 0.5V. Proposed substrate-bias voltage generator is composed of VSS and VBB generator. The former circuit produces negative voltage and supplies its output voltage for VBB generator. As a result VBB generator develops much lower negative voltage than that of conventional one. Proposed circuit is fabricated using 0.18um 1Poly-6Metal CMOS process and measurement result demonstrated stable operation with substrate-bias voltage of -0.95V.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.34-41
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• 1998

An integrated circuit for magnetic stripe storage system is implemented. All the analog and digital circuits are integrated in one chip. The analog block contains preamplifier, peak detecter, comparator and reference generater. And digital block includes reference window signal generater, up/down counter for F/2F signal measurement, bit-error detection logic, and control logic. Both the encoding and decoding functions for F/2F signal processing are provided. An AGC(automatic gain control) circuit which was included in conventional circuits is eliminated due to optimized circuit design. Misreading prevention circuits are also proposed by fixing up new reference bit when broken bits are detected. The prototype chip is implemented using $0.8{\mu}m$ N-well CMOS technology and operates from 3.3 V to 7.5 V of supply voltage. It occupies a die area of $3.04mm^2(1.6mm{\times}1.9mm)$ and dissipates 8 mW with a 5 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.31-38
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• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

• Journal of Digital Convergence
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• v.15 no.5
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• pp.443-451
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• 2017

This paper's objectives are to investigate the criteria for ergonomic evaluation of indoor bike coordinated with virtual images, and to compare HMD-based VR bike with 2D-based one. 12 experts performed delphi method with an aim to determine ergonomic evaluation criteria that were classified into 4 categories(Usability, Emotion, User Values, Reality). 2D-based bike and HMD-based one were compared according to part of final criteria through fuzzy-logic question performed by 20 subjects. Though there were no confidential difference in usability, HMD-based VR bicycle resulted in greater scores than 2D-based one in elements related with emotion, user value and reality statistically. It is expected that this research results will be used as references to evaluate ergonomic design of other indoor exercise equipments combined with VR or AR.

• Journal of Engineering Education Research
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• v.5 no.1
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• pp.27-33
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• 2002

Recently, according to the appearance of various virtual websites using multimedia technologies, the internet applications in engineering education have drawn muchinterests. But unidirectional communication, simple text/image-based webpages and tedious learning process without motivation, etc. have made the lowering of educational efficiency in cyberspace. This paper presents a virtual laboratory system which can be creating efficiencies in the learning process. The proposed virtual laboratory system for digital logic circuits provides interactive learning environment under which the multimedia capabilities of world-wide web can be enhanced. The virtual laboratory system is implemented to describe the on-campus laboratory, the learners can obtain similar experimental data through it. The virtual laboratory system is composed of four important components : principle classroom, simulation classroom, virtual experiment classroom and management system. Learning efficiencies as well as faculty productivity are increased in this innovative teaching and learning environment.