• KOREAN JOURNAL OF CROP SCIENCE
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• v.31 no.3
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• pp.375-382
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• 1986

This study was carried out to obtain the basic information for the clarification of spring growth habits mechanism of naked barleys. The isozyme patterns and activities of peroxidase in the young spike and leaf blade were analyzed during the differentiation and development of young spike. The characteristic differences between the normal and rosetted type were in c and g isozymes in young spike, and in i isozyme in the leaf blade. In the normal type, c and i isozymes disappeared at the stage of spi-kelet differentiation, g isozyme at the stage of flolet differentiation. But, in the rosetted type, those three isozymes remained in dark stained condition until the time of final sampling. Especially, those three isozymes were higher in the rosetted type than those in the normal type even at the stage of bract differentiation(BDS), just prior to the reproductive stage. The activities of peroxidase decreased slowly after BDS in the young spike and leaf blade in the normal type, While, in the rosetted type, increased linearly, and the degree of increasing was remarkable in the young spike. It was interesting that the degree of activities in young spike was higher in the rosetted type than that in the normal type even at BDS. From the above results, the remarkable differences of the isozyme patterns and activities at BDS between the normal and rosetted type were considered to be the physiological expression of the varieties concerned with the degree of spring growth habits.

• The Journal of Advanced Prosthodontics
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• v.6 no.1
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• pp.1-7
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• 2014

PURPOSE. The accuracy of a gypsum model (GM), which was taken using a conventional silicone impression technique, was compared with that of a polyurethane model (PM), which was taken using an iTero$^{TM}$ digital impression system. MATERIALS AND METHODS. The maxillary first molar artificial tooth was selected as the reference tooth. The GMs were fabricated through a silicone impression of a reference tooth, and PMs were fabricated by a digital impression (n=9, in each group). The reference tooth and experimental models were scanned using a 3 shape convince$^{TM}$ scan system. Each GM and PM image was superimposed on the registered reference model (RM) and 2D images were obtained. The discrepancies of the points registered on the superimposed images were measured and defined as GM-RM group and PM-RM group. Statistical analysis was performed using a Student's T-test (${\alpha}=0.05$). RESULTS. A comparison of the absolute value of the discrepancy revealed a significant difference between the two groups only at the occlusal surface. The GM group showed a smaller mean discrepancy than the PM group. Significant differences in the GM-RM group and PM-RM group were observed in the margins (point a and f), mesial mid-axial wall (point b) and occlusal surfaces (point c and d). CONCLUSION. Under the conditions examined, the digitally fabricated polyurethane model showed a tendency for a reduced size in the margin than the reference tooth. The conventional gypsum model showed a smaller discrepancy on the occlusal surface than the polyurethane model.

• Clean Technology
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• v.28 no.1
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• pp.79-93
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• 2022

In this study, an electronics industrial wastewater activated sludge model (e-ASM) to be used as a Water Digital Twin was calibrated based on real high-tech electronics industrial wastewater treatment measurements from lab-scale and pilot-scale reactors, and examined for its treatment performance, effluent quality prediction, and optimal process selection. For specialized modeling of a high-tech electronics industrial wastewater treatment system, the kinetic parameters of the e-ASM were identified by a sensitivity analysis and calibrated by the multiple response surface method (MRS). The calibrated e-ASM showed a high compatibility of more than 90% with the experimental data from the lab-scale and pilot-scale processes. Four electronics industrial wastewater treatment processes-MLE, A2/O, 4-stage MLE-MBR, and Bardenpo-MBR-were implemented with the proposed Water Digital Twin to compare their removal efficiencies according to various electronics industrial wastewater characteristics. Bardenpo-MBR stably removed more than 90% of the chemical oxygen demand (COD) and showed the highest nitrogen removal efficiency. Furthermore, a high concentration of 1,800 mg L^-1 T MAH influent could be 98% removed when the HRT of the Bardenpho-MBR process was more than 3 days. Hence, it is expected that the e-ASM in this study can be used as a Water Digital Twin platform with high compatibility in a variety of situations, including plant optimization, Water AI, and the selection of best available technology (BAT) for a sustainable high-tech electronics industry.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7C
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• pp.678-687
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• 2003

8SQAM(8-state Superposed Quadrature Amplitude Modulation) being a new modem technique for use in power and bandwidth limited digital communication system generates output signals which have a mか and continuous phase transition and a reduced envelope fluctuation by keeping correlation between amplitudes and phases of two subsequent symbols. Also, 8SQAM signal is free of inter-symbol interference(ISI), and has a compact power spectrum. Accordingly 8SQAM, as compared with a conventional 8PSK, is influenced a little by inter-modulation(IM), inter-symbol interference(ISI) and adjacent channel interference(ACI) in a nonlinearly amplified multi-channel(SCPC-FDMA) environment. In this paper, the performance of 8SQAM system in a nonlinearly amplified multi-channel interference environment is analyzed via computer simulation The simulation result shows that 8SQAM outperforms 8PSK with roll-off value of $\alpha$ = 0.3 by 2.7dB in CNR to maintain BER=1$\times$10$^{-4}$ when input back-off(IBO) of HPA is 1dB and channel space is 41.7% of the data bit rate(i.e., spectral efficiency = 2.40b/s/Hz).

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.28 no.2
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• pp.265-271
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• 2010

This paper discusses a new software package, DEM_Comp, developed for effectively compressing large digital elevation model (DEM) data sets based on Lempel-Ziv-Welch (LZW) compression and Huffman coding. DEM_Comp was developed using the $C^{++}$ language running on a Windows-series operating system. DEM_Comp was also tested on various test sites with different territorial attributes, and the results were evaluated. Recently, a high-resolution version of the DEM has been obtained using new equipment and the related technologies of LiDAR (LIght Detection And Radar) and SAR (Synthetic Aperture Radar). DEM compression is useful because it helps reduce the disk space or transmission bandwidth. Generally, data compression is divided into two processes: i) analyzing the relationships in the data and ii) deciding on the compression and storage methods. DEM_Comp was developed using a three-step compression algorithm applying a DEM with a regular grid, Lempel-Ziv compression, and Huffman coding. When pre-processing alone was used on high- and low-relief terrain, the efficiency was approximately 83%, but after completing all three steps of the algorithm, this increased to 97%. Compared with general commercial compression software, these results show approximately 14% better performance. DEM_Comp as developed in this research features a more efficient way of distributing, storing, and managing large high-resolution DEMs.

• The KIPS Transactions:PartA
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• v.10A no.5
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• pp.479-486
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• 2003

As the Internet appliances like digital TV, Internet set-top boxes, and Internet phone, are showing up in the market, the economics of real-time operating system (RTOS), which is an essential for controlling those devices, is expanding faster than ever before. ETRI has developed describes RTOS called Qplus-P, targeting various platforms ranging from PDA to Internet set-top box and home server. This paper describes the implementation of graphic window library for Qplus-P. The Qplus-P graphic window library was implemented using tiny-X graphic server and gtk graphic toolkit, which are open source software. To port this library to various aliances, hangul processing, screen rotation, touch screen, and graphic acceleration functions are added to the tiny-X graphic server of the implementd graphic window library. Currently, Qplus-P graphic window is running on ARM-based appliances such as iPaq PDA, Samsung S3C2400 board, Zaurus PDA, and on Home Server that uses x86 processor. Qplus-P graphic library is provided as a of Qplus-P target builder.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Korean Journal of Remote Sensing
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• v.36 no.5_2
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• pp.867-879
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• 2020

As the era of space technology utilization is approaching, the launch of CAS (Compact Advanced Satellite) 500-1/2 satellites is scheduled during 2021 for acquisition of high-resolution images. Accordingly, the increase of image usability and processing efficiency has been emphasized as key design concepts of the CAS 500-1/2 ground station. In this regard, "CAS 500-1/2 Image Acquisition and Utilization Technology Development" project has been carried out to develop core technologies and processing systems for CAS 500-1/2 data collecting, processing, managing and distributing. In this paper, we introduce the results of the above project. We developed an operation system to generate precision images automatically with GCP (Ground Control Point) chip DB (Database) and DEM (Digital Elevation Model) DB over the entire Korean peninsula. We also developed the system to produce ortho-rectified images indexed to 1:5,000 map grids, and hence set a foundation for ARD (Analysis Ready Data)system. In addition, we linked various application software to the operation system and systematically produce mosaic images, DSM (Digital Surface Model)/DTM (Digital Terrain Model), spatial feature thematic map, and change detection thematic map. The major contribution of the developed system and technologies includes that precision images are to be automatically generated using GCP chip DB for the first time in Korea and the various utilization product technologies incorporated into the operation system of a satellite ground station. The developed operation system has been installed on Korea Land Observation Satellite Information Center of the NGII (National Geographic Information Institute). We expect the system to contribute greatly to the center's work and provide a standard for future ground station systems of earth observation satellites.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).