• Journal of Power Electronics
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• 제15권2호
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• pp.411-418
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• 2015

In this paper, a new method for the online estimation of equivalent series resistances (ESR) of the DC-link capacitors in induction machine (IM) drive systems with a front-end diode rectifier is proposed, where the ESR estimation is conducted during the regenerative operating mode of the induction machine. In the first place, a regulated AC current component is injected into the q-axis current component of the induction machine, which induces the current and voltage ripple components in the DC-link. By processing these AC signals through digital filters, the ESR can be estimated by a recursive least squares (RLS) algorithm. To acquire the AC voltage across the ESR, the DC-link voltage needs to be measured at a double sampling frequency. In addition, the ESR current is simply reconstructed from the stator currents and switching states of the inverter. Experimental results have shown that the estimation error of the ESR is about 1.2%, which is quite acceptable for condition monitoring of the capacitor.

• Journal of Semiconductor Engineering
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• 제2권1호
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• pp.109-118
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• 2021

This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

• Journal of electromagnetic engineering and science
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• 제1권2호
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• pp.131-138
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• 2001

The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

• 한국통신학회논문지
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• 제23권9A호
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• pp.2271-2281
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• 1998

The wordlength optimization for the analog-to-digital converter in DS-CDMA receivers is very important for the efficient implementation of front-end digital demodulator blocks. Wideband CDMA systems reqire a very fast acquisition time, thus they prefer the matched filter base dreceiver architecture.However, the matched filter should san very long chips, and as a results, requires a large number of gates and a high-power consumption. In this paper, the quantization effects on the acquisition performance of the matched filter is analyzed stochastically. The quantization is modeled as a series of saturation and digitization procedures, because the distortion due to the saturation is signal dependent and causes very different effects when compared with that of the, random, digitization noise. Numerical results are obtained to show the optimum saturaton limit of the quantizer for a given wordlength. This analysis can give a guide to low-cost and low-powr digital implementations and assurance of the system performance without intensive simulations.

• ETRI Journal
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• 제29권5호
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• pp.607-613
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• 2007

Most signal-to-noise ratio (SNR) estimation techniques in digital communication channels derive the SNR estimates solely from samples of the received signal after the matched filter. They are based on symbol SNR and assume perfect synchronization and intersymbol interference (ISI)-free symbols. In severe channel distortion where ISI is significant, the performance of these estimators badly deteriorates. We propose an SNR estimator which can operate on data samples collected at the front-end of a receiver or at the input to the decision device. This will relax the restrictions over channel distortions and help extend the application of SNR estimators beyond system monitoring. The proposed estimator uses the characteristics of the second order moments of the additive white Gaussian noise digital communication channel and a linear predictor based on the modified-covariance algorithm in estimating the SNR value. The performance of the proposed technique is investigated and compared with other in-service SNR estimators in digital communication channels. The simulated performance is also compared to the Cram$\acute{e}$r-Rao bound as derived at the input of the decision circuit.

• 한국위성정보통신학회논문지
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• 제2권2호
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• pp.64-68
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• 2007

본 논문에서는 기존의 GPS 항법 신호와 유럽에서 새롭게 추진되고 있는 갈릴레오 위성 항법 신호를 동시에 수신할 수 있는 광대역 고정밀 위성 항법 수신기의 RF 수신단 장치 설계 및 제작 결과에 대하여 기술하고 있다. 고정밀 광대역 위성 항법 수신기는 L - 대역 안테나, 항법 신호별 RF/IF 변환부, 그리고 고성능 기저대역 신호 처리부로 구성되어진다. L - 대역 안테나는 $1.1GHz{\sim}1.6\;GHz$를 수신할 수 있어야 하며, 항법 위성이 지평선 가까이에 있을 경우의 항법 신호를 수신할 수 있어야 한다. 갈릴레오 위성 항법 신호는 L1, E5, E6의 서로 다른 대역의 신호를 가지고 있으며, 신호 대역폭이 20MHz 이상으로 기존의 GPS위성 항법 신호보다 광대역이며, 따라서 수신기의 IF 주파수가 높아지며, 수신기의 처리 속도도 빨라져야 한다. 본 연구에서 개발한 수신기의 RF/IF 변환부는 단일 하향 변환기 구조의 디지털 IF 기술로 설계되었으며, IF 주파수는 위성 항법 신호의 최대 대역폭과 표본화 주파수 등을 고려하여 140MHz로 설정하였으며, 표본화 주파수는 112MHz로 설정하였다. RF/IF 변환부의 최종 출력은 디지털 IF 신호로서, IF 신호를 AD 변환기로 처리하여 얻게 된다. 본 연구에서 설계된 위성 항법용 고정밀 수신기 RF 수신단은 - 130 dBm의 입력 신호에 대하여 40dB Hz 이상의 C/N0 특성을 가지며, 40dB 이상의 동적 범위를 갖도록 자동 이득조절 장치가 포함되어 있다.

• 한국전자파학회논문지
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• 제18권4호
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• pp.379-388
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• 2007

본 논문에서는 사람의 생체 신호를 감지하기 위해 1.6 GHz 단일 채널 도플러 센서와 아날로그 및 디지털 신호 처리부로 구성되어 있는 실시간 호흡 및 심장 박동 감지기를 개발하였다. 도플러 센서의 RF Front End는 발진기, 믹서, 저잡음 증폭기, 브랜치-라인 하이브리드, 그리고 패치 안테나로 구성되어 있다. 센서에 사용된 브랜치-라인 하이브리드는 기존의 하이브리드에 비해 40 % 정도 크기를 줄이면서도 상당히 유사한 성능을 가지도록 인공 전송 선로(artificial transmission line)를 사용하였다. 아날로그 신호처리부는 2차 Sallen-Key 능동 필터를 사용하여 제작되었고 디지털 신호 처리부는 LabVIEW를 사용하여 컴퓨터상에서 구현되었다. 개발된 시스템은 최대 50 cm 거리에서 사람의 호흡과 심장 박동을 측정함으로써 성능을 검증하였다.

• 한국정보통신학회논문지
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• 제11권9호
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• pp.1709-1716
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• 2007

본 논문에서는 고속 동작을 위한 다중 SHA(sample and hold amplifier) 구조의 파이프라인 A/D 변환기(analog-to-digital converter)를 제안하였다. 제안된 구조는 변환 속도를 높이기 위해, 동일한 SHA를 병렬로 하는 다중 SHA를 구성하였다. 이를 비중첩 클럭(nonoverlapping clock)에서 동작하도록 하여 셀을 구성하는 SHA의 수와 비례한 빠른 샘플링 속도를 얻을 수 있도록 하였다. 제안된 구조를 적용하여 VDSL(very high-speed digital subscriber line) 모뎀의 아날로그 front-end단의 요구 사항을 만족하는 파이프라인 A/D 변환기를 설계하였다. 설계된 A/D 변환기의 DNL(differential nonlinearity)과 INL(integral nonlinearity)은 각각 $0.52LSB{\sim}-0.50LSB,\;0.80LSB{\sim}-0.76LSB$의 특성을 나타내어 설계 사양을 만족함을 확인하였다. 또한 2048 point 대한 FFT를 수행한 결과 SNR이 약 66dB로 10.7비트의 해상도가 얻어짐을 확인하였으며, 전력 소모는 24.32mW로 측정되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.