• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.10a
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• pp.183-187
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• 2008

This paper describes a power control scheme to improve the performance of a fuel cell battery hybrid power source for residential application. The proposed power control scheme includes a power control strategy to control the power flow of the fuel cell hybrid power system and a digital control technique for a front-end dc-dc converter of the fuel cell. The power control strategy enables the fuel cell to operate within the high efficiency region defined by the polarization curve and efficiency curve of the fuel cell. A dual boost converter with digital control is applied as a front-end dc-dc converter to control the fuel cell output power. The digital control technique of the converter employs a moving-average digital filter into its voltage feedback loop to cancel the low frequency harmonic current drawn from the fuel cell and then limits the fuel cell output current to a current limit using a predictive current limiter to keep the fuel cell operation within the high efficiency region as well as to minimize the fuel cell oxygen starvation.

• Journal of IKEEE
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• v.18 no.1
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• pp.172-178
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• 2014

This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the $SpO_2$ value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a $0.11{\mu}m$ CMOS technology and has 4 level of gain properties. The occupied area is $0.174mm^2$.

• Journal of Sensor Science and Technology
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• v.31 no.2
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• pp.115-119
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• 2022

A readout circuit for a mercury-cadmium-telluride (MCT)-amplified mid-wave infrared (IR) photodetector was realized and applied to noncontact chemical agent detectors based on a quantum cascade laser (QCL). The QCL emitted 250 times for each wavelength in 0.2-㎛ steps from 8 to 12 ㎛ with a frequency of 100 kHz and duty ratio of 10%. Because of the nonconstant QCL emission power during on-duty, averaging the photodetector signals is essential. Averaging can be performed in digital back-end processing through a high-speed analog-to-digital converter (ADC) or in analog front-end processing through an integrator circuit. In addition, it should be considered that the 250 IR data points should be completely transferred to a PC during each wavelength tuning period of the QCL. To average and minimize the IR data, we designed a readout circuit using the analog front-end processing method. The proposed readout circuit consisted of a switched-capacitor integrator, voltage level shifter, relatively low-speed analog-to-digital converter, and micro-control unit. We confirmed that the MCT photodetector signal according to the QCL source can be accurately read and transferred to the PC without omissions.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.95-117
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• 2006

In this paper, we describe the optimization of the link-level performance and the complexity of floating-point and fixed-point methods in IEEE 802.16e OFDMA/TDD mobile modem. In floating-point design, we propose the channel estimation methods for downlink traffic channel and select the optimized method using computer simulation. So we also propose efficent algorithms for time and frequency synchronization, Digital Front End and CINR estimation scheme to optimize the system performance. Furthermore, we describe fixed-point method of uplink traffic and control channels. The superiority of the proposed algorithm is validated using the performances of Detection, False Alarm, Missing Probability and Mean Acquisition Time, PER Curve, etc. For fixed-point design, we propose an efficient methodology for optimized fixed-point design from floating-point At last, we design fixed-point of traffic channel, time and frequency synchronization, DFE block in uplink and downlink. The tradeoff between performance and complexity are optimized through computer simulations.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.753-758
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• 2002

In this paper, low voltage 3V CMOS programmable gain amplifier(PGA) for using in the transmitter and receiver of ADSL analog front-end is designed. The designed receive PGA is connected with 1.1MHz continuous lowpass fillet and controls the gain from 0dB to 30dB. And also the transmitter PGA is connected with 138KHz lowpass filter and controls the gain from -15dB to 0dB. The gain of All PGAs can be programmed by digital logic circuits and main controller. The designed PGAs are verified using HSPICE simulation with $0.35\mu{m}$ CMOS parameter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Journal of IKEEE
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• v.13 no.1
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• pp.41-48
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• 2009

This paper describes an implementation of the analog front end (AFE) incorporated with the image signal processing (ISP) unit in the SoC, dominating the performance of the CCD image sensor system. New schemes are exploited in the high-frequency sampling to reduce the sampling uncertainty apparently as the frequency increases, in the structure for the wide-range variable gain amplifier (VGA) capable of $0{\sim}36\;dB$ exponential gain control to meet the needed bandwidth and accuracy by adopting a new parasitic insensitive capacitor array. Moreover, the double cancellation of the black-level noise was efficiently achieved both in the analog and the digital domain. The proposed topology fabricated in a $0.35-{\mu}m$ CMOS process was proved in a full CCD camera system of 10-bit accuracy, dissipating 80 mA at 15 MHz with a 3.3 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.220-228
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• 1995

An optimized 4-stage 12-bit pipelined CMOS analog-to-digital converter (ADC) architecture is proposed to obtain high linearity and high yield. The ADC based on a multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted-capacitor (BWC) array in the front-end stage and a unit-capacitor (UC) array in the back-end stages to improve integral nonlinearity (INL) and differential nonlinearity (DNL) simultaneously whil maintaining high yield. A digital-domain nonlinear error calibration technique is applied in the first stage of the ADC to improve its accuracy to 12-bit level. The largest DNL error in the mid-point code of the ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is simulated to prove the effectiveness of the proposed ADC architecture.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.210-216
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• 2004

In this paper, we propose a noncoherent On-Off Keying (OOK) Ultra Wide Band (UWB) system based on power detection with noise power calibration for low power applications. The proposed UWB system achieves good bit error rate performance which is favorably comparable to that of the system using the ideal adaptive threshold, while maintaining simple receiver structure, In addition, low power Analog Front-End (AFE) blocks for the proposed noncoherent UWB transceiver are proposed and verified using CMOS technology. Simulation results on the pulse generator, delay time generator and 1-bit Analog-to-Digital (AID) converter show feasibility of the proposed UWB AFE system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.