• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.443-447
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• 2001

The PLL synthesizer is used often in communication system due to several merits, such as broad bandwidth, high accuracy and stability of frequency. But it is difficult to use in torrent digital communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed frequency synthesizer that generate the clock frequency randomly at a high speed using the DDS technology and is applied to the pattern generator system for digital image.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.1-6
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• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.903-911
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• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.2
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• pp.168-175
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• 1987

In this paper, a FFH-SS hybrid communication method using digital frequency synthesizer is proposed. This can simultaneously share the same frequency band with conventional band limited communication method without interference. In the experiment the selective hopping pattern is attained by some conbination of serial to parallel conversion of maximal code from pseudo random noise generater, and it is observed that the selective hopping band transition can be more easily achieved when the hop interval is nonuniform than it is uniform. Digital frequency synthesizer is now reported to have very poor spurious suppression ability below 50~60dB, the reason of this is observed from the experimental result, and the way of how to solve this problem is presneted.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.985-988
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• 1999

This paper describes the architecture and the IC implementation of a Direct Digital Frequency Synthesizer (DDFS). That is based on an angle rotation algorithm (CORDIC). It is shown that the architecture can be implemented as a multipliers, feedfoward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 0.35${\mu}{\textrm}{m}$ SAMSUNG KG90 Library.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1987.04a
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• pp.201-205
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• 1987

In FH-SS systems when the bopping band is enough wide to onerlap with conventional band limited communication cethod (CBM). The portion of suchacts as an interfering signal. Thus it is gard to use them all together. This paper presents how the frequency gopping systems can simultaneously share the same band with CBM. The proposed mithod is that the frequency gopping band can arbitraily controlled by setting the specific input bith of digital frequency synthesizer to logical zero state We realized this by putting the hopping band Controller between pseudeo random generater and frequency synthesizer.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.45-48
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• 1999

The demands of WLAN(Wireless Local Area Network) systems increase rapidly in whole society and this phenonenon has been expected that WLAN wi11 substitute for wired-LAN. The FHSS(Frequency Hopped Spread Spectrum) method using the WLAN is changed to the performance of Frequency synthesizer. In this paper, we proposed pipeline-accumulator using ring-counter method instead of constant accumulator that has demerits of size and power consumption. Designed DDFS generated operating frequency of 167MHz and maximum output frequency of 83.5MHz.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.2
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• pp.126-137
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. And we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.361-368
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• 2003

A new high-speed direct digital frequency synthesizer using a low power pipelined parallel accumulator is proposed. The proposed pipelined parallel accumulator uses both pipelining and paralleling techniques to increase speed and to reduce power consumption. The 2-pipelined 2-parallel accumulator only consumes 66% and 69% power of the 4-pipelined accumulator and the 4-parallel accumulator respectively with the same throughput. The proposed accumulator can achieve higher throughput with smaller area and less power consumption in lower clock frequency. All circuit simulations and implementations are based on a 0.35um CMOS process with VCC = 3.3V.