• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.240-245
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• 2019

Phase interpolation is widely adopted in frequency synthesizers and clock-and-data recovery systems to produce an intermediate phase from two existing phases. The intermediate phase is typically generated by combining two input phases with different weights. Unfortunately, this results in non-uniform phase steps. Alternatively, the intermediate phase can be generated by successive approximation, where the interpolated phase at each approximation stage is obtained using the same weight for the two intermediate phases. As a proof of concept, this study presents a 2-GHz 8-bit successive approximation digital-to-phase converter that is designed using 65-nm CMOS technology. The converter receives an 8-phase clock signal as input, and the most significant bit (MSB) section selects four phases to create two sinusoidal waveforms using a harmonic rejection filter. The remaining least significant bit (LSB) section applies the successive approximation to generate the required intermediate phase. Monte-Carlo simulations show that the proposed converter exhibits 0.46-LSB integral nonlinearity and 0.31-LSB differential nonlinearity with a power consumption of 3.12 mW from a 1.2-V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.586-589
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• 2003

Repeater is developed. Based on the systems The up-converter of the WCDMA Digital Optic pecifications, the structure of the up-converter is accomplished and its block diagram is drawn. The up-converter is implemented according to these block diagrams. Subsequently the low pass filter, the automatic level controlled attenuator, the frequency synthesizer and other components for the up-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the up-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• Journal of the Korea Computer Industry Society
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• v.2 no.8
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• pp.1063-1068
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• 2001

In this paper, we designed a high resolution six channel DSB modulator of Acousto-Optic effect generator make use of DDS technology. Also, configured seamless connection for other instruments to use IEEE-488 bus interface. We programmed the device driver for DDS and DAC control by 80C51 assembler language. And, high resolution 6 channel DSB modulator has improved the important characteristics of that the frequency tuning range, the resolution, the switching time. This DSB modulator system can use high precision frequency synthesizer for instruments.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.3
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• pp.41-51
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• 1997

In this study, two types of the direct digital frequency synthesizers (DDFS) designed and implemented using 1.0.mu.m CMOS gatearray(SOG) technolgoies are interoduced. To analize the effect of the number of phase bits(L), address data bits(A), and DAC bits (D) on the output spectrums of the DDFSs, the NCO-based BCD-DDFS composed of L=24, A=14, and D=8, and the improved binary-DDFS composed of L=24, A=8, and D=10 have been studied. The chips have been designed with and without a noise shapper to reduce spurious noises due to phase truncation and reduced sine ROM in output spectrum.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.9 no.1
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• pp.30-38
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• 1984

In this paper, we designed the programmable 2nd order switched capacitor filter that the center frequency can be varied linearly with the clock frequency, and that the peak gaion and the selectivity can be controlled with digital signal by the capacitor array. In addition, speech synthesizer system was constructed with this filter, korean consonants being synthesized. Therefore, this filter shows the possibility that most Korean language sounds can be synthesized in the real time mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.615-618
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• 2006

The broadband power detector for direct- onversion Six-port output circuit was designed and implementaed in this paper. The power detector should linearly operated to produce the linear amplitude and phase signal fer input RF signal in required broadband. So, the power detector should be designed under conditions of matching circuit with low VSWR. The designed power detectors, which were implemented in L-band with 50 ohm matching and Ku-band with matching circuit and isolator, respectively, were evaluated in the performances.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.217-218
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• 2008

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.

• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.381-389
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• 2015

A fully integrated multistandard multiband CMOS mobile TV tuner with small silicon area and low power consumption is proposed for receiving multiple mobile digital TV signals and FM signal. In order to reduce the silicon area of the multistandard multiband receiver, other RF front-end circuits except LNAs are shared and a local oscillator (LO) signal generation architecture with a single VCO for a frequency synthesizer is proposed. To reduce the low frequency noise and the power consumption, a vertical NPN BJT is used in an analog baseband circuits. The RF tuner IC is implemented in a $0.18-{\mu}m$ CMOS technology. The RF tuner IC satisfies all specifications for DVB-H/T, T-DMB, and ISDB-T with a sufficient margin and a successful demonstration has been carried out for DVB-H/T, T-DMB, and ISDB-T with a digital demodulator.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.