• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• ETRI Journal
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• 제37권5호
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• pp.961-971
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• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권2호
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• pp.601-617
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• 2014

In digital radio broadcasting systems, long delays are incurred in service start time when tuning to a particular frequency because several synchronization steps, such as symbol timing synchronization, frame synchronization, and carrier frequency offset and sampling frequency offset compensation are necessary. Therefore, the operation of the synchronization blocks causes delays ranging from several hundred milliseconds to a few seconds until the start of the radio service after frequency tuning. Furthermore, if spectrum inversed signals are transmitted in digital radio broadcasting systems, the receivers are unable to decode them, even though most receivers can demodulate the spectral inversed signals in analog radio broadcasting systems. Accordingly, fast synchronization techniques and a method for spectral inversion detection are required in digital radio broadcasting systems that are to replace the analog radio systems. This paper presents a joint detection method of frame, integer carrier frequency offset, and spectrum inversion for DRM Plus digital broadcasting systems. The proposed scheme can detect the frame and determine whether the signal is normal or spectral inversed without any carrier frequency offset and sampling frequency offset compensation, enabling fast frame synchronization. The proposed method shows outstanding performance in environments where symbol timing offsets and sampling frequency offsets exist.

• 한국통신학회논문지
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• 제33권5C호
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• pp.386-394
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• 2008

디지털 홀로그래픽 비디오 시스템을 제작하기 위해서는 디지털 홀로그램을 가능한 빠르게 생성하는 것이 중요하다. 본 논문에서는 디지털 홀로그램의 전체 좌표를 대상으로 반복적인 가산 연산을 이용하여 Fresnel 홀로그램의 생성 속도를 높이는 알고리듬을 제안한다. 디지털 홀로그램을 계산하기 위한 3차원 객체는 컴퓨터 그래픽(computer graphic, CG)으로 제작한 깊이영상(depth-map image)을 이용하였다. 본 논문에서 제안하는 알고리듬은 부동소수점 형식의 반복가산기법을 이용하여 디지털 홀로그램의 위상을 고속으로 계산하는 기법이다. 실험결과 제안한 알고리듬은 일반적인 CGH 수식을 이용한 기법의 70%, [3]에서 제안한 기법보다 30%이상 연산속도가 빨라졌다.

• 전기전자학회논문지
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• 제22권4호
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• pp.1158-1162
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• 2018

안티-하모닉락 기능을 가지는 고속-락킹 MDLL 기반의 디지털 클락 주파수 증배기를 소개한다. 제안하는 디지털 주파수 증배기는 하모닉락 문제 없이 빠른 락킹 시간을 구현하기 위하여 새로운 MSB-구간 검색 알고리즘을 사용한다. 제안하는 디지털 MDLL 주파수 증배기는 65nm CMOS 공정으로 설계되었으며, 1 GHz ~ 3 GHz의 출력 동작주파수 영역을 가진다. 제안하는 디지털 MDLL은 프로그래머블한 N/M (N=1, 4, 5, 8, 10, M=1, 2, 3)의 분수배 주파수 증배 기능을 제공한다. 제안하는 MDLL은 1GHz에서 3.52 mW의 전력을 소모하고, 14.07 ps의 피크-투-피크 (p-p) 지터를 갖는다.

• Journal of information and communication convergence engineering
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• 제10권2호
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• 전자공학회논문지SC
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• 제37권3호
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• pp.33-43
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• 2000

특이섭동 기법을 이용한 제어 시스템의 설계가 가능하기 위해서는 무엇보다도, 빠른 동력학의 안정성이 중요하다. 그런데, 제어기의 디지털 구현으로 인하여, 이 빠른 동력학의 안정도가 영향을 받을 수 있다. 본 논문은 최근의 개발된 우수한 성능의 특이섭동 기반의 STT 자동조정장치(autopilot) 설계의 경우를 들어 이러한 특이섭동 기법에 기반하여 설계된 제어 시스템에 대한 샘플링 영향을 조사하고 개선된 제어기 설계의 예를 제시하여, 특이섭동 기반 제어 시스템 에 대한 샘플링 영향 분석의 필요성 및 유효성을 밝혔다.

• Journal of information and communication convergence engineering
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• 제9권1호
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• pp.95-99
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• 2011

Digital forensics is the emerging research field for determining digital forgeries. Key issues of the tampered images are to solve the problems for detecting the interpolation factor and the tampered regions. This paper describes a method to detect the interpolation factors and the forged maps using the differential method and fast Fourier transform(FFT) along the horizontal, vertical, and diagonal direction, respectively from digital filtered tampered images. The detection map can be used to find out interpolated regions from the tempered image. Experimental results demonstrate the proposed algorithm proves effective on several filtering images by adobe $Photoshop^{TM}$ and show a ratio of detecting the interpolated regions and factors from digital filtered composite images.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.131-134
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• 1988

This Paper describes a algorithm for evaluating the loss of load probability of a generating system using Fast Hartley Transform. The Fast Hartley Transform(FHT) Is as fast as or faster than the Fast Fourier Transform(FHT) and serves for all the uses such as spectral, digital processing and convolution to which the FFT is at present applied. The method has been tested by applying to IEEE reliability test system and the effectiveness is demonstrated.

• 한국항행학회논문지
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• 제21권4호
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• pp.402-412
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• 2017

방송 기술과 통신 기술의 융합은 유비쿼터스 네트워크를 위한 핵심 기술 중 하나이다. 본 논문에서는 AT-DMB(advanced terrestrial digital multimedia broadcasting) 방송망과 통신망의 융합망을 제안하고, MIIS(media independent information server/service)를 통한 방송 시스템과 통신 시스템 간 연동을 제공하는 융합 시스템을 제안한다. 특히, 방송통신 융합망에서 QoS(Quality of Service)와 전력절감의 향상을 위한 fast wakeup and connection 기술을 제안한다. 제안하는 기술은 사용자 단말의 휴지기 인터페이스로 유입되는 서비스 지연과 해당 인터페이스의 전력소모를 최소화하는 기술이다. 끝으로, 시뮬레이션 및 성능분석을 통해 제안하는 기술이 서비스 지연을 감소시키면서 전력소모를 최소화할 수 있음을 확인하였다.