• Title/Summary/Keyword: Digital Fast

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Detection of Visual Attended Regions in Road Images for Assisting Safety Driving (안전 운전 지원을 위한 도로 영상에서 시각 주의 영역 검출)

  • Kim, Jong-Bae
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.49 no.1
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    • pp.94-102
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    • 2012
  • Recently entered into an aging socity as the number of elderly drivers is increasing. Traffic accidents of elderly drivers are caused by driver inattentions such as poor vehicle control due to aging, visual information retrieval problems caused by presbyopia, and objects identifying problems caused by low contrast sensitivity. In this paper, detection method of ROIs on the road is proposed. The proposed method creates the saliency map to detect the candidate ROIs from the input image. And, the input image is segmented to obtain the ROIs boundary. Finally, selective visual attention regions are detected according to the presence or absence of a segmented region with saliency pixels. Experimental results from a variety of outdoor environmental conditions, the proposed method presented a fast object detection and a high detection rate.

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 ㎛ CMOS

  • Cho, Sunghun;Lee, DongSoo;Lee, Juri;Park, Hyung-Gu;Pu, YoungGun;Yoo, Sang-Sun;Hwang, Keum Cheol;Yang, Youngoo;Park, Cheon-Seok;Lee, Kang-Yoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.3
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    • pp.274-286
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    • 2016
  • This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

A Study on Development of Fashion Sharing Platform for Shared Economy -Focusing on fashion rental service case- (공유경제를 위한 패션 공유플랫폼 활성화 방안 연구 -패션 대여서비스 사례를 중심으로-)

  • Yoon, Ji-Yeon;Kim, Seung-In
    • Journal of the Korea Convergence Society
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    • v.8 no.7
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    • pp.199-205
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    • 2017
  • Despite the economic downturn, the amount of clothing being discarded is increasing due to the fast fashion. The purpose of this study is to propose a fashion sharing service development to settle the rational consumption culture along with the abandoned clothes problem. Shared fashion rental service has attracted as a solution to environmental problems not only when clothes are incinerated but also in manufacturing process, but there is a lack of precedent research. Therefore, this study is meaningful in that it has developed two development plans based on the results of analysis of service case based on three factors by Rachel Botsman. First, active community development. Second, it is the creation of goods through activation of the shared economy. In this study, there are limitations that can't be proved through actual application, so more research is needed through empirical studies on actual users in the future.

Accuracy and precision of integumental linear dimensions in a three-dimensional facial imaging system

  • Kim, Soo-Hwan;Jung, Woo-Young;Seo, Yu-Jin;Kim, Kyung-A;Park, Ki-Ho;Park, Young-Guk
    • The korean journal of orthodontics
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    • v.45 no.3
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    • pp.105-112
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    • 2015
  • Objective: A recently developed facial scanning method uses three-dimensional (3D) surface imaging with a light-emitting diode. Such scanning enables surface data to be captured in high-resolution color and at relatively fast speeds. The purpose of this study was to evaluate the accuracy and precision of 3D images obtained using the Morpheus 3D$^{(R)}$ scanner (Morpheus Co., Seoul, Korea). Methods: The sample comprised 30 subjects aged 24.34 years (mean $29.0{\pm}2.5$ years). To test the correlation between direct and 3D image measurements, 21 landmarks were labeled on the face of each subject. Sixteen direct measurements were obtained twice using digital calipers; the same measurements were then made on two sets of 3D facial images. The mean values of measurements obtained from both methods were compared. To investigate the precision, a comparison was made between two sets of measurements taken with each method. Results: When comparing the variables from both methods, five of the 16 possible anthropometric variables were found to be significantly different. However, in 12 of the 16 cases, the mean difference was under 1 mm. The average value of the differences for all variables was 0.75 mm. Precision was high in both methods, with error magnitudes under 0.5 mm. Conclusions: 3D scanning images have high levels of precision and fairly good congruence with traditional anthropometry methods, with mean differences of less than 1 mm. 3D surface imaging using the Morpheus 3D$^{(R)}$ scanner is therefore a clinically acceptable method of recording facial integumental data.

A 500MSamples/s 6-Bit CMOS Folding and Interpolating AD Converter (500MSamples/s 6-비트 CMOS 폴딩-인터폴레이팅 아날로그-디지털 변환기)

  • Lee Don-Suep;Kwack Kae-Dal
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.7
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    • pp.1442-1447
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    • 2004
  • In this paper, a 6-Bit CMOS Folding and Interpolating AD Converter is presented. The converter is considered to be useful as an integrated part of a VLSI circuit handling both analog and digital signals as in the case of HDD or LAN applications. A built-in analog circuit for VLSI of a high-speed data communication requires a small chip area, low power consumption, and fast data processing. The proposed folding and interpolating AD Converter uses a very small number of comparators and interpolation resistors, which is achieved by cascading a couple of folders working in different principles. This reduced number of parts is a big advantage for a built-in AD converter design. The design is based on 0.25m double-poly 2 metal n-well CMOS process. In the simulation, with the applied 2.5V and a sampling frequency of 500MHz, the measurements are as follows: power consumption of 27mw, INL and DNL of $\pm$0.1LSB, $\pm$0.15LSB each, SNDR of 42dB with an input signal of 10MHz.

Low-Complexity Handheld 3-D Scanner Using a Laser Pointer (단일 레이저 포인터를 이용한 저복잡도 휴대형 3D 스캐너)

  • Lee, Kyungme;Lee, Yeonkyung;Park, Doyoung;Yoo, Hoon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.64 no.3
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    • pp.458-464
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    • 2015
  • This paper proposes a portable 3-D scanning technique using a laser pointer. 3-D scanning is a process that acquires surface information from an 3-D object. There have been many studies on 3-D scanning. The methods of 3-D scanning are summarized into some methods based on multiple cameras, line lasers, and light pattern recognition. However, those methods has major disadvantages of their high cost and big size for portable appliances such as smartphones and digital cameras. In this paper, a 3-D scanning system using a low-cost and small-sized laser pointer are introduced to solve the problems. To do so, we propose a 3-D localization technique for a laser point. The proposed method consists of two main parts; one is a fast recognition of input images to obtain 2-D information of a point laser and the other is calibration based on the least-squares technique to calculate the 3-D information overall. To verified our method, we carry out experiments. It is proved that the proposed method provides 3-D surface information although the system is constructed by extremely low-cost parts such a chip laser pointer, compared to existing methods. Also, the method can be implemented in small-size; thus, it is enough to use in mobile devices such as smartphones.

Fabrication of EEG Measuring System with High Precision Characteristics (고정밀도의 뇌파측정시스템 개발 연구)

  • 도영수;장호경;한병국
    • Progress in Medical Physics
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    • v.13 no.3
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    • pp.156-162
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    • 2002
  • In this study, we attempted in preparing high precision EEG measuring equipment. To measure EEG in high efficiency, pre-amplifier should get high performance common mode rejection ratio. Also, separation amplifier is essential to eliminate common line noise. So, our study were pointed at elevating the efficiency of eliminating noise, user safety and low noise characteristics. Prepared high precision pre-amplifier for EEG was A/D converted to automatically classify $\alpha$ wave, $\beta$ wave and $\theta$ wave. And converted data were Fast Fourier Transformed with real time DSP (Digital Signal Processing). Clinical demonstrations were carried out with healthy students, aged between 20 to 26 who has no histories of illness. To recognize the efficiency of the EEG, prepared EEG were used with MS equipment in low stimulated state and high stimulated state. Then, we studied at the effect of sensitivity on brain wave. From this study, it is known that our EEG equipment is efficient in sensitivity evaluation and suitable stimulations for each psychological state are required.

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Real-Time Motion Tracking Detection System for a Spherical Pendulum Using a USB Camera (USB 카메라를 이용한 실시간 구면진자 운동추적 감지시스템)

  • Moon, Byung-Yoon;Hong, Sung-Rak;Ha, Manh-Tuan;Kang, Chul-Goo
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.40 no.9
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    • pp.807-813
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    • 2016
  • Recently, a spherical pendulum attached to an end-effector of a robot manipulator has been frequently used for a test bed of residual vibration suppression control in a multi-dimensional motion. However, there was no automatic tracking system to detect the current bob position on-line, and there was inconvenience to not be able to store the bob position in real time and plot the trajectory. In this study, we developed a two-dimensional, real-time bob-detecting system using a digital USB camera, of which the key is hardware component design and software C programming for fast image processing and interfacing. The developed system was applied to residual vibration suppression control of a two-dimensional spherical pendulum that is attached at the end-effector of a two degree-of-freedom SCARA robot, and the effectiveness of the developed system has been demonstrated.

A Low-power DIF Radix-4 FFT Processor for OFDM Systems Using CORDIC Algorithm (CORDIC을 이용한 OFDM용 저전력 DIF Radix-4 FFT 프로세서)

  • Jang, Young-Beom;Choi, Dong-Kyu;Kim, Do-Han
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.45 no.3
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    • pp.103-110
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    • 2008
  • In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

A Study on Design and Performance Evaluation of the Frequency Snthesizer Using the DDS in the Transmitter of the FFH/BFSK System (FFH/BFSK 시스템 송신부에서 DDS를 이용한 주파수합성기 설계 및 성능평가에 관한 연구)

  • 이두석;유형렬;정지원;조형래;김기문
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.11a
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    • pp.161-166
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    • 1999
  • The global trends of mobile communication system is moving toward digitizing, high-speed and large-capacity. Also, to utilize the limited frequency-resource efficiently, spread spectrum system is a mainstream. In this study we are concerning with the fast frequency-hopping system. Instead of the PLL with many problems such as phase-noise, we used the DDS is popular in these days minimizes the disadvantage of PLL. In the case the FFH system is designed using the PLL, it is difficult to be satisfied of the design conditions such as RF badwidth and the settling time of PLL, and it has limitation because of complex circuit by using the balanced modulator. In this study, we evaluated the performance in order to design the FFH system using the DDS. The system that has the improvement of error rate, 1Mhps hopping rate and 5MHz RF bandwidth is designed and evaluated.

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