• Journal of Power Electronics
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• v.18 no.5
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• ETRI Journal
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• v.37 no.5
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• pp.961-971
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• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.2
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• pp.601-617
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• 2014

In digital radio broadcasting systems, long delays are incurred in service start time when tuning to a particular frequency because several synchronization steps, such as symbol timing synchronization, frame synchronization, and carrier frequency offset and sampling frequency offset compensation are necessary. Therefore, the operation of the synchronization blocks causes delays ranging from several hundred milliseconds to a few seconds until the start of the radio service after frequency tuning. Furthermore, if spectrum inversed signals are transmitted in digital radio broadcasting systems, the receivers are unable to decode them, even though most receivers can demodulate the spectral inversed signals in analog radio broadcasting systems. Accordingly, fast synchronization techniques and a method for spectral inversion detection are required in digital radio broadcasting systems that are to replace the analog radio systems. This paper presents a joint detection method of frame, integer carrier frequency offset, and spectrum inversion for DRM Plus digital broadcasting systems. The proposed scheme can detect the frame and determine whether the signal is normal or spectral inversed without any carrier frequency offset and sampling frequency offset compensation, enabling fast frame synchronization. The proposed method shows outstanding performance in environments where symbol timing offsets and sampling frequency offsets exist.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.386-394
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• 2008

For digital holographic video system, it is important to generate digital hologram as fast as possible. This paper proposed a fixed-point method and fast generation method that can calculate the Fresnel hologram using operation of whole-coordinate recursive addition. To compute the digital hologram, 3D object is assumed to be a collection of depth-map point generated using a PC. Our algorithm can compute a phase on a hologram by recursive addition with fixed-point format at a high speed. When we operated this algorithm on a personal computer, we could maximally compute digital hologram about 70% faster than conventional method and about 30% faster than of [3]'s method.

• Journal of IKEEE
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• v.22 no.4
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• pp.1158-1162
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• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.33-43
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• 2000

The guarantee of the fast dynamics stability is essential for successful application of singular Perturbation technique to control systems design. Even though the fast dynamics of the control systems is rendered stable by an analog controller, the fast dynamics stability of the control systems resulted from an digital implementation of the analog controller can be impaired severely. In this paper, we first investigate the time sampling effects on singular perturbation based control systems by centering on a design example of recently developed singular perturbation based STT missile autopilot with high performance. The investigation shows that the stability margin the fast dynamics of the STT misile autopilot system decreases rapidly as the sampling interval of discretizing the analog autopilot increases. Under this analysis, we propose a composite digital controller with compensation for the decreasing stability margin of the fast dynamics due to time sampling to achieve better performance with respect to sampling time. The improved performance of the proposed composite digital controller is verified by simulation. This result shows that one needs to investigate time sampling effects in the digital implementation of singular perturbation based controllder, and then can have benefit from the investigation.

• Journal of information and communication convergence engineering
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• v.9 no.1
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• pp.95-99
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• 2011

Digital forensics is the emerging research field for determining digital forgeries. Key issues of the tampered images are to solve the problems for detecting the interpolation factor and the tampered regions. This paper describes a method to detect the interpolation factors and the forged maps using the differential method and fast Fourier transform(FFT) along the horizontal, vertical, and diagonal direction, respectively from digital filtered tampered images. The detection map can be used to find out interpolated regions from the tempered image. Experimental results demonstrate the proposed algorithm proves effective on several filtering images by adobe $Photoshop^{TM}$ and show a ratio of detecting the interpolated regions and factors from digital filtered composite images.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.131-134
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• 1988

This Paper describes a algorithm for evaluating the loss of load probability of a generating system using Fast Hartley Transform. The Fast Hartley Transform(FHT) Is as fast as or faster than the Fast Fourier Transform(FHT) and serves for all the uses such as spectral, digital processing and convolution to which the FFT is at present applied. The method has been tested by applying to IEEE reliability test system and the effectiveness is demonstrated.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.402-412
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• 2017

The convergence of broadcasting and telecommunication technologies is a key issue of the ubiquitous networks. So this paper offers the convergence of integrated telecommunication networks and broadcasting system, Advanced Terrestrial Digital Multimedia Broadcasting (AT-DMB), and the interconnection of them via the Media Independent Information Server/Service (MIIS). Then, this paper proposes the fast wakeup and connection mechanism with concepts for improving QoS and energy efficiency simultaneously. In the proposed convergence network, our mechanism places the key on the minimization of both the incoming service delay destined to a turned-off interface by using the broadcasting network and the additional energy consumption. This paper further evaluates the performance of proposed mechanism through the numerical and experimental analysis and has confirmed the decrease of both service delay and energy consumption.