• Journal of Positioning, Navigation, and Timing
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• v.6 no.4
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• pp.211-221
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• 2017

Ellipsodially referenced survey (ERS) is considered as one of the challenging issues in the hydrographic surveys due to the fact that the bathymetric data collected by this technique can be readily transformed either to the geodetic or the chart datum by application of some geoscientific models. Global Navigation Satellite Systems (GNSS) is a preferred technique to determine the ellipsoidal height of a vessel reference point (RP) because it provides cost-effective and unprecedentedly accurate positioning solutions. Especially, the GNSS-derived heights include heave and dynamic draft of a vessel, so as for the reduced bathymetric solutions to be potentially free from these corrections. Although over the last few decades, differential GNSS (DGNSS) has been widely adopted in the bathymetric surveys, it only provides limited accuracy of the vertical component. This technical barrier can be effectively overcome by adopting the so-called GNSS carrier phase (CPH) based techniques, enhancing accuracy of the height solution up to few centimeters. From the positioning algorithm standpoint, the CPH-based techniques are categorized under absolute and relative positioning in post-processing mode; the former is precise point positioning (PPP) correcting errors by the global or regional models, the latter is post-processed kinematic positioning (PPK) that uses the differencing technique to common error sources between two receivers. This study has focused on assessment of achievable accuracy of the ellipsoidal heights obtained from these CPH-based techniques with a view to their applications to hydrographic surveys where project area is, especially, few tens to hundreds kilometers away from the shore. Some field trials have been designed and performed so as to collect GNSS observables on static and kinematic mode. In this paper, details of these tests and processed results are presented and discussed.

• Journal of Navigation and Port Research
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• v.28 no.8
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• pp.715-719
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• 2004

This paper deals with EMC filter for a personal computer(PC). A PC contains many sources of noise inside and out, with many connected cables. High noise levels are also emitted from the PC because of high-speed signals. So radiated noise from the computer body may sometimes cause problems. Therefore, we design and fabricate an electromagnetic compatibility (EMC) filter for PC, which is composed of feed-through capacitors and ferrite beads with high permeability. Through extensive test, the proposed EMC filter is shown to have excellent differential-mode and common-mode noises filtering characteristics above 30 dB in the frequency band from 10 MHz to 1.5 GHz. The immunity characteristics are improved more than 10 to 30 dB over the frequency band from DC to 1.8 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.19-27
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• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• Journal of the Korean Society of Propulsion Engineers
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• v.3 no.4
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• pp.12-22
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• 1999

Operation of an electromagnetic shaker system using a Class-D amplifier may cause unacceptable electromagnetic interference to another electronic system, requiring the user to take whatever steps are necessary to correct the interference. A differential amplifier in a Class-D amplifier is used to decrease the effect of a common-mode noise voltage in a shaker system. To prevent a ground loop, a transformer is inserted in another shaker system. These methods show reduction of the unwanted vibration which has occurred before. A transformer in a charge amplifier was used to prevent a ground loop in a shaker system using a Class-AB amplifier a few years ago, but it was susceptible of noise in a shaker system using a Class-D amplifier. Hence we corrected a ground loop between a charge amplifier and a vibration control/analysis system without a transformer. The usefulness of this approach is illustrated by the results of experiments.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.31 no.2 s.257
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• pp.188-194
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• 2007

New diesel engines equipped with common-rail injection systems and advanced engine management control allow drastic decreases in the production of particulate matters and nitrogen oxides with a significant advantage in terms of the fuel consumption and $CO_2$ emissions. Nevertheless, the contribution of exhaust gas after treatment in the ultra low emission vehicles conception has become unavoidable today. Recently the passive type DPF(Diesel Particulate Filter Trap) system for diesel passenger vehicle has been manufactured into mass production from a French automotive maker since the year of 2000. This passive DPF system fully relies on the catalytic effects from additives blended into the diesel fuel and additives injected into the DPF system. In this study, the effects of PM regeneration in the commercial diesel passenger vehicle with the passive type DPF system were investigated in chassis dynamometer CVS(constant volume sampler)-75 mode. As shown in this experimental results, the DPF regeneration was observed at temperature as low as $350^{\circ}C$. And the engine-controlled the DPF regeneration founded to be one of the most promising regeneration technologies. Moreover, the durability of this DPF system was evaluated with a season weather in terms of the differential pressure and exhaust gas temperature traces from a road test during the total mileage of 80,000km.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1379-1385
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• 2009

We propose a low-power and high-speed client receiver for a mobile display digital interface (MDDI) newly in this paper. The low-power receiver is designed such that bias currents, sink and source currents, are insensitive to variations of power supply, process, temperature, and common-mode input voltage (VCM) and is able to operate at a rate of 450Mbps or above under the conditions of a power supply range of 3.0 to 3.6Vand a temperature range of -40 to 85$^{\circ}$C. And it is confirmed by a simulation result that the current dissipation is less than 500${\mu}$A. A test chip is manufactured with the Magna chip 0.35${\mu}$m CMOS process. When a test was done, the data receiver and data recovery circuits are functioning normally.

• Journal of Animal Science and Technology
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• v.64 no.4
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• pp.752-769
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• 2022

Wheat gluten is an increasingly common ingredient in poultry diets but its impact on the small intestine in chicken is not fully understood. This study aimed to identify effects of high-gluten diets on chicken small intestines and the variation of their associated transcriptional responses by age. A total of 120 broilers (Ross Strain) were used to perform two animal experiments consisting of two gluten inclusion levels (0% or 25%) by bird's age (1 week or 4 weeks). Transcriptomics and histochemical techniques were employed to study the effect of gluten on their duodenal mucosa using randomly selected 12 broilers (3 chicks per group). A reduction in feed intake and body weight gain was found in the broilers fed a high-gluten containing diet at both ages. Histochemical photomicrographs showed a reduced villus height to crypt depth ratio in the duodenum of gluten-fed broilers at 1 week. We found mainly a significant effect on the gene expression of duodenal mucosa in gluten-fed broilers at 1 week (289 differentially expressed genes [DEGs]). Pathway analyses revealed that the significant DEGs were mainly involved in ribosome, oxidative phosphorylation, and peroxisome proliferator-activated receptor (PPAR) signaling pathways. These pathways are involved in ribosome protein biogenesis, oxidative phosphorylation and fatty acid metabolism, respectively. Our results suggest a pattern of differential gene expression in these pathways that can be linked to chronic inflammation, suppression of cell proliferation, cell cycle arrest and apoptosis. And via such a mode of action, high-gluten inclusion levels in poultry diets could lead to the observed retardation of villi development in the duodenal mucosa of young broiler chicken.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.