• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.405-413
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• 2013

In this paper, a high-reliability differential paired 24-bit eFuse OTP memory with program-verify-read mode for PMICs is designed. In the proposed program-verify-read mode, the eFuse OTP memory can do a sensing margin test with a variable pull-up load in consideration of programmed eFuse resistance variation and can output a comparison result through a PFb (pass fail bar) pin by comparing a programmed datum with its read one. It is verified by simulation results that the sensing resistance is lower with $4k{\Omega}$ in case of the designed differential paired eFuse OTP memory than $50k{\Omega}$ in case of its dual-port eFuse OTP memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.722-725
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• 2012

In this paper, we design an 8-bit eSuse OTP (one-time programmable) memory based on a $0.35{\mu}m$ BCD process using differential paired eFuse cells which can sense BL data without a reference voltage and also have smaller sensing resistances of programmed eFuse links. The channel widths of a program transistor of the differential eFuse OTP cell are splitted into $45{\mu}m$ and $120{\mu}m$. Also, we implement a sensing margin test circuit with variable pull-up loads in consideration of variations of the programmed eFuse resistances. It is confirmed by measurement results that the designed 8-bit eFuse OTP memory IP gives a better yield when the channel width is $120{\mu}m$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.2
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• pp.107-115
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• 2015

In this paper, a small-area 32-bit differential paired eFuse OTP memory for power ICs is designed. In case of smaller number of rows than that of columns for the OTP memory cell array, a scheme for the cell array reducing the number of SL driver circuits requiring their larger layout areas by routing the SL (source line) lines supplying programming currents for eFuse links in the row direction instead of the column direction as well as a core circuit is proposed. In addition, to solve a failure of being blown for non-blown eFuse links by the electro-migration phenomenon, a regulated voltage of V2V ($=2V{\pm}0.2V$) is used to a RWL (read word line) driver circuit and a BL (bit line) pull-up driver circuit. The layout size of the designed 32-bit eFuse OTP memory is $228.525{\mu}m{\times}105.435{\mu}m$, which is confirmed to be 20.7% smaller than that of the counterpart using the conventional cell array routing, namely $197.485{\mu}m{\times}153.715{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2359-2368
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• 2013

In this paper, an IRD (internal read data) circuit preventing the reentry into the read mode while keeping the read-out DOUT datum at power-up even if noise such as glitches occurs at signal ports such as an input signal port RD (read) when a power IC is on, is proposed. Also, a pulsed WL (word line) driving method is used to prevent a DC current of several tens of micro amperes from flowing into the read transistor of a differential paired eFuse OTP cell. Thus, reliability is secured by preventing non-blown eFuse links from being blown by the EM (electro-migration). Furthermore, a compared output between a programmed datum and a read-out datum is outputted to the PFb (pass fail bar) pin while performing a sensing margin test with a variable pull-up load in consideration of resistance variation of a programmed eFuse in the program-verify-read mode. The layout size of the 8-bit eFuse OTP IP with a $0.18{\mu}m$ process is $189.625{\mu}m{\times}138.850{\mu}m(=0.0263mm^2)$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1734-1740
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• 2012

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).