• Title/Summary/Keyword: Differential Amplifier

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A Study on the Design of Amplifier for Source Driver IC applicable to the large TFT-LCD TV (대형 TFT-LCD TV에 적용 가능한 Source Driver IC 감마보정전압 구동용 앰프설계에 관한 연구)

  • Son, Sang-Hee
    • Journal of IKEEE
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    • v.14 no.2
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    • pp.51-57
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    • 2010
  • A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

A Design of Low-Power Wideband Bipolar Current Conveyor (CCII) and Its Application to Universal Instrumentation Amplifiers (저전력 광대역 바이폴라 전류 콘베이어(CCII)와 이를 이용한 유니버셜 계측 증폭기의 설계)

    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.5
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    • pp.143-152
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    • 2004
  • A novel low-power wideband bipolar second-generation current conveyors(CCIIs) and its application to universal instrumentation amplifier(UIA) were proposed. The CCII for accuracy voltage or current transfer characteristics and low current input impedance adopted adaptive current bias circuit into conventional class Ab CCII. The UIA consists of only two CCIIs and four resistors. Three instrumentation function of the UIA can be realized by selection of input signals and resistors. The simulation results show that the CCII has input impedance of 2.0$\Omega$ and the voltage gain of 60㏈ for frequency range from 0 to 50KHz when used as a voltage amplifier. The CCII has also good characteristics of current follower for current range from -100㎃ to +100㎃. The simulation results show that the UIA has three instrumentation amplifier functions without resistor matching. The UIA has the voltage gain of 40㏈ for frequency range from 0 to 100KHz when used as a fully-differential instrumentation amplifier. The power dissipations of the CCII and the UIA are 0.75㎽ and 1.5㎽ at supply voltage of $\pm$2.5V, respectively.

A 12b 10MS/s CMOS Pipelined ADC Using a Reference Scaling Technique (기준 전압 스케일링을 이용한 12비트 10MS/s CMOS 파이프라인 ADC)

  • Ahn, Gil-Cho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.16-23
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    • 2009
  • A 12b 10MS/s pipelined ADC with low DC gain amplifiers is presented. The pipelined ADC using a reference scaling technique is proposed to compensate the gain error in MDACs due to a low DC gain amplifier. To minimize the performance degradation of the ADC due to amplifier offset, the proposed offset trimming circuit is employed m the first-stage MDAC amplifier. Additional reset switches are used in all MDACs to reduce the memory effect caused by the low DC gain amplifier. The measured differential and integral non-linearities of the prototype ADC with 45dB DC gain amplifiers are less than 0.7LSB and 3.1LSB, respectively. The prototype ADC is fabricated in a $0.35{\mu}m$ CMOS process and achieves 62dB SNDR and 72dB SFDR with 2.4V supply and 10MHz sampling frequency while consuming 19mW power.

Full CMOS PLC SoC ASIC with Integrated AFE (Analog Frond-End 내장형 전력선 통신용 CMOS SoC ASIC)

  • Nam, Chul;Pu, Young-Gun;Park, Joon-Sung;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.10
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    • pp.31-39
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    • 2009
  • This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

0.18 μm CMOS Power Amplifier for Subgigahertz Short-Range Wireless Communications (Sub-GHz 근거리 무선통신을 위한 0.18 μm CMOS 전력증폭기)

  • Lim, Jeong-Taek;Choi, Han-Woong;Lee, Eun-Gyu;Choi, Sun-Kyu;Song, Jae-Hyeok;Kim, Sang-Hyo;Lee, Dongju;Kim, Wansik;Kim, Sosu;Seo, Mihui;Jung, Bang-Chul;Kim, Choul-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.29 no.11
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    • pp.834-841
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    • 2018
  • A power amplifier for subgigahertz short-range wireless communication using $0.18-{\mu}m$ CMOS technology is presented. It is designed as a differential structure to form easily a virtual ground node, to increase output power, and to design a cascode structure to prevent breakdown. The transistor gate width was determined to maximize the output power and power-added efficiency(PAE), and the balun was optimized through electromagnetic simulation to minimize the loss caused by the matching network. This power amplifier had a gain of more than 49.5 dB, a saturation power of 26.7 dBm, a peak PAE of 20.7 % in the frequency range of 860 to 960 MHz, and a chip size of $2.14mm^2$.

Design of 0.5V Electro-cardiography (전원전압 0.5V에서 동작하는 심전도계)

  • Sung, Min-Hyuk;Kim, Jea-Duck;Choi, Seong-Yeol;Kim, Yeong-Seuk
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.7
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    • pp.1303-1310
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    • 2016
  • In this paper, electrocardiogram (ECG) analog front end with supply voltage of 0.5V has been designed and verified by measurements of fabricated chip. ECG is composed of instrument amplifier, 6th order gm-C low pass filter and variable gain amplifier. The instrument amplifier is designed to have gain of 34.8dB and the 6th order gm-C low pass filter is designed to obtain the cutoff frequency of 400Hz. The operational transconductance amplifier of the low pass filter utilizes body-driven differential input stage for low voltage operation. The variable gain amplifier is designed to have gain of 6.1~26.4dB. The electrocardiogram analog front end are fabricated in TSMC $0.18{\mu}m$ CMOS process with chip size of $858{\mu}m{\times}580{\mu}m$. Measurements of the fabricated chip is done not to saturate the gain of ECG by changing the external resistor and measured gain of 28.7dB and cutoff frequency of 0.5 - 630Hz are obtained using the supply voltage of 0.5V.

Potentiostat circuits for amperometric sensor (전류법 기반 센서의 정전압 분극 장치 회로)

  • Lim, Shin-Il
    • Journal of Sensor Science and Technology
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    • v.18 no.1
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    • pp.95-101
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    • 2009
  • A simple and new CMOS potentiostat circuit for amperometric sensor is described. To maintain a constant potential between the reference and working electrodes, only one differential difference amplifier (DDA) is needed in proposed design, while conventional potentiosatat requires at least 2 operational amplifiers and 2 resistors, or more than 3 operational amplifiers and 4 resistors for low voltage CMOS integrated potentiostat. The DDA with rail-to-rail design not only enables the full range operation to supply voltage but also provides simple potentiostat system with small hardwares and low power consumption.

Simple desing of FIR filters using resistor array (저항열을 이용한 간단한 FIR 필터의 설계방법)

  • 김제우;김진규;조민형
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.31B no.9
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    • pp.22-26
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    • 1994
  • In this paper a method of designing FIR filters without digital arithmetic operationsi is persented. The filter coefficients are represented by resistors combined with a differential amplifier. With this method an FIR filter can be simply impemented without refering to complex digital arithmetic operations. Furthermore, in this scheme, no additional D/A converter is needed for D/A conversion. Spectral response response of a pulse shaping filter of 17 coefficients is shown as an illustration.

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A Signal Process Circuit for ISFET Biosensor and A Desitgn for Their One-Chip Integration (ISFET 바이오센서에의 적용을 위한 신호처리회로의 개발과 그들의 단일칩 집적설계)

  • Hwa Il Seo;Won Hyeong Lee;Soo Won Kim
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.1
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    • pp.46-51
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    • 1991
  • The new signal process circuit using ISFETs as two input devices of a MOS differential amplifier stage for application to a ISFET biosensor was developed and its operational characteristics simulated. For a single chip integration of ISFETs, developed signal process circuit and metal reference electrode, serial studies including process development and chip layout was carried out.

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A Development of Seam Tracker by one Chip Microprocessor (궤적 기억이 가능한 용접선 추적장치의 개발)

  • Ahn, B. W.;Noh, C. J.;Park, S. K.
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.32 no.1
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    • pp.78-84
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    • 1996
  • Recently, the fact that welding conditions are dangerous for men and the shapes of seams are complex enforced the welding system to be automatic. In order to obtain this target, are chip Microprocessor controlled welding system is devised in this study. The tracking of seam shape is achieved by applying a differential transformer and by using a program developed. This welding system mainly consists of a sensor, the differential transformer, a servo power amplifier, a control system, and DC motors. It is verified that the developed welding system is able to track three kinds of seam shapes.

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