• Journal of the Optical Society of Korea
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• 제18권2호
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• pp.167-173
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• 2014

A novel multi-oxide layer structure for vertical cavity surface emitting laser (VCSEL) structures is proposed to achieve higher single mode output power. The structure has four oxide layers with different aperture sizes and thicknesses. The oxide layer thicknesses are optimized simultaneously to reach the highest single mode output power. A heuristic method is proposed for plotting the influence of these variable changes on the operation of optical output power. A comprehensive optical-electrical thermal-gain self-consistent VCSEL model is used to simulate the continuous-wave operation of the multi-layer oxide VCSELs. A comparison between optimized VCSELs with different structures is presented. The results show that by using multi-oxide layers with different thicknesses, higher single-mode optical output power could be achieved in comparison with multi-oxide layer structures with the same thicknesses.

• Transactions on Electrical and Electronic Materials
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• 제18권5호
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• pp.250-252
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• 2017

High-performance full swing logic inverters were fabricated using amorphous 1 wt% Si doped indium-zinc-oxide (a-SIZO) thin films with different channel layer thicknesses. In the inverter configuration, the threshold voltage was adjusted by varying the thickness of the channel layer. The depletion mode (D-mode) device used a TFT with a channel layer thickness of 60 nm as it exhibited the most negative threshold voltage (-1.67 V). Inverters using enhancement mode (E-mode) devices were fabricated using TFTs with channel layer thicknesses of 20 or 40 nm with excellent subthreshold slope (S.S). Both the inverters exhibited high voltage gain values of 30.74 and 28.56, respectively at $V_{DD}=15V$. It was confirmed that the voltage gain can be improved by increasing the S.S value.

• 한국세라믹학회지
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• 제47권5호
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• pp.461-466
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• 2010

In this study, $Al_2O_3/TaAlO_4/SiO_2$ (A/TAlO/S) structures with tantalum aluminate charge trap layer were fabricated for Nand flash memory device. We evaluated the memory window and retention characteristic as the thickness of the tunnel oxide was varied among 3 nm, 4 nm, and 5 nm. All tunnel oxide thicknesses were measured by ellipsometer and TEM (Transmission Electron Microscope). The A/TAlO/S multi-layer film consisted of 5 nm tunnel oxide showed the best result of memory window of 1.57 V and retention characteristics. After annealing the 5 nm tunnel oxide A/TAlO/S multi-layer film at $900^{\circ}C$. The memory window decreased to 1.32 V. Moreover, the TEM images confirmed that the thickness of multi-layer structure decreased 14.3% after annealing and the program conditions of A/TAlO/S multi-layer film decreased from 13 V to 11 V for 100 ms. Retention properties of both as-deposited and annealed films stably maintained until to $10^4$ cycles.

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.253-256
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• 2010

Different active layer thicknesses for zinc oxide (ZnO) bottom-contact thin-film transistors (TFTs) were fabricated with a poly-4-vinyphenol polymeric dielectric using injector type atomic layer deposition. The properties of the ZnO TFTs were influenced by the active thickness and width-to-length (W/L) ratio of the device. The threshold voltage of ZnO TFTs shifted positively as the active layer thickness decreased, while the subthreshold slope decreased. The W/L ratio of ZnO TFTs also affected the mobility and subthreshold slope. An optimized TFT structure exhibited an on-tooff current ratio of above 106 with solid saturation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• 한국재료학회지
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• 제21권1호
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• pp.34-38
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• 2011

In this study, the effects of an annealed buffer layer with different thickness on heterojunction diodes based on the ZnO/ZnO/p-Si(111) systems were reported. The effects of an annealed buffer layer with different thickness on the structural, optical, and electrical properties of zinc oxide (ZnO) films on p-Si(111) were also studied. Before zinc oxide (ZnO) deposition, different thicknesses of ZnO buffer layer, 10 nm, 30 nm, 50 nm and 70 nm, were grown on p-Si(111) substrates using a radio-frequency sputtering system; samples were subsequently annealed at $700^{\circ}C$ for 10 minutes in $N_2$ in a horizontal thermal furnace. Zinc oxide (ZnO) films with a width of 280nm were also deposited using a radio-frequency sputtering system on the annealed ZnO/p-Si (111) substrates at room temperature; samples were subsequently annealed at $700^{\circ}C$ for 30 minutes in $N_2$. In this experiment, the structural and optical properties of ZnO thin films were studied by XRD (X-ray diffraction), and room temperature PL (photoluminescence) measurements, respectively. Current-voltage (I-V) characteristics were measured with a semiconductor parameter analyzer. The thermal tensile stress was found to decrease with increasing buffer layer thickness. Among the ZnO/ZnO/p-Si(111) diodes fabricated in this study, the sample that was formed with the condition of a 50 nm thick ZnO buffer layer showed a strong c-axis preferred orientation and I-V characteristics suitable for a heterojunction diode.

• 한국세라믹학회지
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• 제49권6호
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• pp.631-636
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• 2012

Conventional SONOS (poly-silicon/oxide/nitride/oxide/silicon) type memory is associated with a retention issue due to the continuous demand for scaled-down devices. In this study, $Al_2O_3/Y_2O_3/SiO_2$ (AYO) multilayer structures using a high-k $Y_2O_3$ film as a charge-trapping layer were fabricated for nonvolatile memory applications. This work focused on improving the retention properties using a $Y_2O_3$ layer with different tunnel oxide thickness ranging from 3 nm to 5 nm created by metal organic chemical vapor deposition (MOCVD). The electrical properties and reliabilities of each specimen were evaluated. The results showed that the $Y_2O_3$ with 4 nm $SiO_2$ tunnel oxide layer had the largest memory window of 1.29 V. In addition, all specimens exhibited stable endurance characteristics (program/erasecycles up to $10^4$) due to the superior charge-trapping characteristics of $Y_2O_3$. We expect that these high-k $Y_2O_3$ films can be candidates to replace $Si_3N_4$ films as the charge-trapping layer in SONOS-type flash memory devices.

• 한국표면공학회지
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• 제47권4호
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• pp.155-161
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• 2014

The present work is concerned with the formation behavior of anodic oxide films on Al7075 alloy under a galvanostatic condition in 20 vol.% sulfuric acid solution. The formation behaviour of anodic oxide films was studied by the analyses of voltage-time curves and observations of colors, morphologies and thicknesses of anodic films with anodization time. Hardness of the anodic oxide films was also measured with anodization time and at different positions in the anodic films. Six different stages were observed with anodiziation time : barrier layer formation (stage I), pore formation (stage II), growth of porous films (stage III), abnormal rapid oxide growth (stage IV), growth of non-uniform oxide films (stage V) and breakdown of the thick oxide films under high anodic voltages (stage VI). Hardness of the anodic oxide films appeared to decrease with increasing anodization time and with the position towards the outer surface. This work provides useful information about the thickness, uniformity, imperfections and hardness distribution of the anodic oxide films formed on Al7075 alloy in sulfuric acid solution.

• 한국수소및신에너지학회논문집
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• 제24권2호
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• pp.186-192
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• 2013

In order to reduce the costs and to improve the durability of solid oxide fuel cell (SOFC), the operating temperature should be decreased while the power density is maintained as much as possible. However, lowering the operating temperature increases the cathode interfacial polarization resistances dramatically, limiting the performance of low-temperature SOFC at especially purely electronic conducting cathode. To improve cathode performance at low temperature, the number of reaction sites for the oxygen reduction should be increased by using a mixed ionic and electronic conducting (MIEC) material. In this study, anode-supported fuel cells with two different thicknesses of the MIEC cathode were fabricated and tested at various operating temperatures. The anode supported cell with $32.5{\mu}m$-thick BSCFZn-LSCF cathode layer showed much lower polarization resistance than that with $3.2{\mu}m$ thick cahtode and higher power density especially at low temperature. The effects of cathode layer thickness on the electrochemical performance are discussed with analysis of impedance spectra.

• 전기학회논문지
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• 제58권12호
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• pp.2425-2430
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• 2009

Dye-sensitized solar cell(DSC) is composed of a dye-adsorbed nanoporous $TiO_2$ layer on fluorine-doped tin oxide(FTO) glass substrate, electrolyte, and platinium doped counter electrode. Among these, a dye-absorbed nanoporous $TiO_2$ layer plays an important role in the performance of the DSC because the injected electrons from excited dye molecules move through this layer. And the condition of $TiO_2$ layer such as the morphology and thickness affects on the electron movement. Therefore, the performances and the efficiency of DSC change as the thickness of $TiO_2$ layer is different. Electrochemical Impedance Spectroscopy(EIS) is the powerful analysis method to study the kinetics of electrochemical and photoelectrochemical processes occurring in the DSC especially the injected electron movements. So we analyzed the DSCs with different $TiO_2$ thicknesses by using EIS to understand the influence of the $TiO_2$ thickness to the performance of the DSC clearly. Finally, we got the EIS analysis on the DSC with different $TiO_2$ thickness from the internal resistance of the DSC, the electron life time and the amount of dye molecules.