• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of the Korean Vacuum Society
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• v.8 no.1
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• pp.75-82
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• 1999

Ion energy is one of the crucial property in thin film deposition by internal ICP assisted I-PVD. As ion energy is determined by the difference between the plasma potential and the substrate bias potential, ICP excitation frequency was tested with medium frequency of 4 MHz and two types of tuning circuits, alternate and floating LC network with a biasing resistor, were tested. The results showed that plasma potential was less than 5 V in a range of Ar pressures, 5mTorr to 30 mTorr, at 4 MHz RF 600 W and 60 V of maximum RF antenna voltage was maintained either at RF input or output terminal. By proper control of RLC circuit installed after after RF antenna, 50V of RF induced voltage on RF antenna was obtained at 500W input power. The total impedance of RF antenna and plasma was around 10$\Omega$, and minimum RF voltage was obtained with a condition of lowest reactance at most 0.05$\Omega$.

• Korean Journal of Optics and Photonics
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• v.16 no.3
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• pp.266-274
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• 2005

We have designed photonic crystal based bandpass filters whose characteristics are suitable for WDM communication system. The filters consist of coupled point defect resonators in two-dimensional photonic crystal. The frequency response of coupled resonators has been analyzed by the coupling of modes in time, from which the design parameters for the coupled resonator filters have been extracted. For the appropriate choice of the design parameters, each resonator is treated as a lumped L-C resonance circuit, and from the analogy between the equivalent circuit and the standard L-C filter circuits, the design parameters are simply determined from the table for general filter circuit design. Based on the determined design parameters, a photonic crystal based filter has been designed and its performance has been calculated using the finite-difference time-domain method. The designed filter shows a pass band of 50GHz and 0.5 dB in-band ripple, which is suitable for typical WDM communication systems with 100GHz channel spacing.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.63-70
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• 2020

In this paper, the transmit-receive module for military seekers has been designed and fabricated in 35 GHz. To increase the performance of substrates and high integration of circuits in millimeter-wave band, a 4-layer LCP(Liquid Crystal Polymer) substrate was developed. This substrate was implemented with three FCCL substrates and two adhesive layers, and a process using the difference in melting point between the substrates was used for lamination. Using a strip line and a microstrip line was confirmed by the transmission loss along the length of the substrate, and the performance of LCP substrates was validated with a power divider in 35 GHz. After confirming the performance of individual blocks such as power amplifier and low noise amplifier, a single channel Ka-band transmission/reception module was developed using a 4-layer liquid crystal polymer substrate. The transmit power of this module has above 1.1W in pulse duty 10% and has an output power of 1.1W and it has receive noise figure less than 8.5 dB and receive gain more than 17.6 dB.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.4 s.107
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• pp.380-386
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• 2006

Electric fuel sender fur the vehicle fuel gauge system was designed and fabricated based on the CPW(Co-Planer Waveguide) transmission line theory. It is applied on this system that characteristic impedance of RF transmission line can be varied by the surrounded material of the line. By the characteristic impedance owing the level of gasoline or diesel fuel in vehicle fuel tank, CPW line has corresponding reflected signal as much as changed impedance. Detected signal is amplified, and delivered to fuel indicator into cluster unit on dash board. Conventional floating mechanical buoy level gauge has several defects as low reliability and high break down rate by mechanical operation, and has not good linearity for the fuel level difference. CPW line with electric circuits are constructed on 1.6 mm thickness epoxy substrate, and measurement shows that this system has more accurate level and better linearity than conventional mechanical system. New electric fuel sender which has good productivity with long lifetime and low-in-cost by the SMT chip assembling could be replaced this system with conventional floating buoy system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.420-423
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• 2015

This paper proposes a method of non-linearity error detection and calibration for binary-weighted charge-driven DACs. In general, the non-linearity errors of DACs often occur due to the mismatch of layout designs or process variation, even when careful layout design methods and process calibration are adopted. Since such errors can substantially degrade the SNDR performance of DAC, it is crucial to accurately measure the errors and calibrate the design mismatches. The proposed method employs 2 identical DAC circuits. The 2 DACs are sweeped, respectively, by using 2 digital input counters with a fixed difference. A comparator identifies any non-linearity errors larger than an acceptable discrepancy. We also propose a calibration method that can fine-tune the DAC's capacitor sizes iteratively until the comparator finds no further errors. Simulations are presented, which show that the proposed method is effective to detect the non-linearity errors and calibrate the capacitor mismatches of a 12-bit DAC design of binary-weighted charge-driven structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10A
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• pp.969-979
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• 2002

This paper proposes an novel method of minimizing Interference which causes data decision error in digital wireless communications. In this method, in order to suppress ISI which is caused by the phase difference between the transmitted and received signal phases, the transmitted and received signals are always kept orthogonal by compensating the transmitted signal for detecting the phase noise and the delay of the received signal was implemented by MOS circuits. To delay the phase of the signal, additive white Gaussian noise (AWGN) environment was used. The phase and delay of the signal transmitted through AWGN channel were compensated in the modulator of the transmitter and the compensated signal was demodulated using quasi-direct conversion receiver and QPSK demodulator. ISI suppression was achieved by keeping the orthogonality between the compensated transmitted signal and the receive signal. The error probability of data decision was compared. By simulation the proposed system was proved to be effective in minimizing the ISI.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.