• Journal of dental hygiene science
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• v.23 no.2
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• pp.176-184
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• 2023

Background: Recently, a piezoelectric ultrasonic scaler based on a feedback control mechanism was introduced for pain relief. This study aimed to investigate the effects of a new ultrasonic scaler in reducing pain and discomfort in adults. Methods: A newly introduced ultrasonic scaler (Master 700^®) was used as the test device and a conventional ultrasonic scaler device (PIEZON^®) was used as the control device. Forty-one healthy adults visited the dental clinic for dental scaling but did not undergo scaling or periodontal treatment within 6 months. Intraoral examinations were performed before scaling and 3 months later; before scaling, both devices were randomly assigned on the left or right side of each dentition (split-mouth model) and scaling was performed by a registered dental hygienist. The levels of pain and discomfort during scaling were evaluated subjectively and objectively using the visual analog scale (VAS) and physiological monitoring of the heart rate (HR), respectively. Time was measured for each device. Results: All clinical indicators, except bleeding on probing, significantly improved with both devices. The treatment times were 7 minutes, 13 minutes (control) and 6 minutes, 59 minutes (test). VAS scores for pain were 4.89±2.12 (control) and 4.58±2.77 (test) points out of 10; for noise, these were 4.68±2.33 (control) and 4.55±2.55 (test), and for vibration, the values were 4.26±2.0 (control) and 4.18±2.48 (test). HR averages were 72.34±3.39 (control) and 75.97±9.78 (test) beats/min. No statistically significant differences were observed between the devices. Conclusion:The pain, discomfort levels, and scaling time of the new piezoelectric ultrasonic scaler did not differ from those of the conventional device. Further research and development are necessary for more prominent pain-relief effects of scaling devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.275-278
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• 2002

As the gate lengths of MOSFETs are scaled down to sub-50nm regime, there are key issues to be considered in the device design. In this paper, we have investigated the characteristics of threshold voltage for MOSFET device. We have simulated the MOSFETs with gate lengths from 100nm to 30nm using generalized scaling. Then, we have known the device scaling limits for nano structure MOSFET. We have determined the threshold voltages using LE(Linear Extraction) method.

• International Journal of Contents
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• v.9 no.3
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• pp.9-14
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• 2013

In this paper, we will examine single face tracking algorithms with scaling function in a mobile device. Face detection and tracking either in PC or mobile device with scaling function is an unsolved problem. Standard single face tracking method with particle filter has a problem in tracking the objects where the object can move closer or farther from the camera. Therefore, we create an algorithm which can work in a mobile device and perform a scaling function. The key idea of our proposed method is to extract the average of skin color in face detection, then we compare the skin color distribution between the detected face and the tracking face. This method works well if the face position is located in front of the camera. However, this method will not work if the camera moves closer from the initial point of detection. Apart from our weakness of algorithm, we can improve the accuracy of tracking.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.92-97
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• 2008

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Journal of Digital Contents Society
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• v.10 no.2
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• pp.217-223
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• 2009

In order to decrease the power consumption in Embedded Linux environment based on XScale PXA255, We produce the device driver of DFS(Dynamic Frequency Scaling) technique, design and implement the middleware DFM(Dynamic Frequency Management) to scale the power of embedded target board with porting this device drive, suggest the method to reduce the Embedded system's power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.442-446
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.494-497
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• 2002

In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model(QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll-off characteristics for threshold voltage of MOSFET with decreasing channel length, we know u value must be nearly 1 in the generalized scaling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.311-316
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• 2001

The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. At devices become smaller from submicron to nanometer, we have investigated MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and also newEPI MOSFET for improved structure to weak point of LDD structure by TCAD(Technology Computer Aided Design) to develop optimum device structure. We analyzed and compared the EPI device characteristics such as impart ionization, electric field and I-V curve with those of lightly-doped drain(LDD) MOSFET. Also, we presented that TCAD simulator is suitable for device simulation and the scaling theory is suitable at nano structure device.