• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.5
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• pp.353-360
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• 2012

As semiconductor device technology continuously shrinks, low-open area etch process prevails in front-end etch process, such as contact etch as well as one cylindrical storage (OCS) etch. To eliminate over loaded wafer processing test, it is commonly performed to emply diced small coupons at stage of initiative process development. In nominal etch condition, etch responses of whole wafer test and coupon test may be regarded to provide similar results; however, optical emission spectroscopy (OES) which is frequently utilize to monitor etch chemistry inside the chamber cannot be regarded as the same, especially etch mask is not the same material with wafer chuck. In this experiment, we compared OES data acquired from two cases of etch experiments; one with coupon etch tests mounted on photoresist coated wafer and the other with coupons only on the chuck. We observed different behaviors of OES data from the two sets of experiment, and the analytical results showed that careful investigation should be taken place in OES study, especially in coupon size etch.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.71-78
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• 2012

This paper describes trends in conventional scaling compared with advanced technologies such as 3D integration (3DI) and bumpless through-silicon via (TSV) processes, as well as the characteristics of CMOS (Complementary Metal Oxide Semiconductor) Logic device after thinning the wafers to less than $10{\mu}m$. Each module process including thinning, stacking, and TSV, is optimized for 3D Wafer-on-Wafer (WOW) application. Optimization results are discussed with valuable data in detail. Since vertical wiring of bumpless TSV can be connected directly to the upper and lower substrates by self-alignment, bumps are not necessary when TSV interconnects are used.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.11-15
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• 2013

The wafer bonding process becomes a flexible approach to material and device integration. The bonding strength in 3-dimensional process is crucial factor in various interface bonding process such as silicon to silicon, silicon to metals such as oxides to adhesive intermediates. A measurement method of bonding strength was proposed by utilizing AFM applied CNT probe tip which indicated the relative simplicity in preparation of sample and to have merit capable to measure regardless type of films. Also, New Tool was utilized to measure of tip radius. The cleaned $SiO_2$-Si bonding strength of SPFM indicated 0.089 $J/m^2$, and the cleaning result by RCA 1($NH_4OH:H_2O:H_2O_2$) measured 0.044 $J/m^2$, indicated negligible tolerance which verified the possibility capable to measure accurate bonding strength. And it could be confirmed the effective bonding is possible through SPFM cleaning.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.6
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• pp.48-54
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• 2012

In recent years, developments in the semiconductor and electronic industries have brought a rapid increase in the use of large size silicon. However, for many companies, it is hard to produce 400mm or 450mm wafers, because of excesive funds for exchange the equipments. Therefore, it is necessary to investigate 300mm wafer to obtain a better efficiency and a good property rate. Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This research investigated the surface characteristics that apply variable machining conditions and Taguchi Method was used to obtain more flexible and optimal condition. In this study, the machining conditions have head speed, oscillation speed and polishing time. By using optimum condition, it achieves a ultra precision mirror like surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.109-110
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• 2007

Plasma etching process에서 magnetic field 영향에 관한 연구이다. High level dry etch process를 위해서는 high density plasma(HDP)가 요구된다. HDP를 위해서 MERIE(Magnetical enhancement reactive ion etcher) type의 설비가 사용되며 process chamber side에 4개의 magnetic coil을 사용한다. 이런 magnetic factor가 특히 wafer edge부문에 plasma charging에 의한 damage를 유발시키고 이로 인해 device Vth(Threshold voltage)가 shift 되면서 제품의 program 동작 문제의 원인이 되는 것을 발견하였다. 이번 연구에서 magnetic field와 관련된 plasma charge damage를 확인하고 damage free한 공정조건을 확보하게 되었다.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.6 s.171
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• pp.144-151
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• 2005

Spin coater is regarded as a major module rotating at high speed to be used build up polymer resin thin film layer fur bonding process of GaAs wafer. This module is consisted of spin unit for spreading uniformly, align device, resin spreading nozzle and et. al. Specially, spin unit which is a component of module can cause to vibrate and finally affect to the uniformity of polymer resin film layer. For the stability prediction of rotation velocity and uniformity of polymer resin film layer, it is very important to understand the dynamic characteristics of assembled spin coater module and the dynamic response mode resulted from rotation behavior of spin chuck. In this paper, stress concentration mode and the deformed shape of spin chuck generated due to angular acceleration process are presented using analytical method for evaluation of structural safety according to the revolution speed variation of spin unit. And also, deformation form of GaAs wafer due to dynamic behavior of spin chuck is presented fur the comparison of former simulated results.

• Journal of Powder Materials
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• v.28 no.1
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• pp.25-30
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• 2021

The surface of silicon dummy wafers is contaminated with metallic impurities owing to the reaction with and adhesion of chemicals during the oxidation process. These metallic impurities negatively affect the device performance, reliability, and yield. To solve this problem, a wafer-cleaning process that removes metallic impurities is essential. RCA (Radio Corporation of America) cleaning is commonly used, but there are problems such as increased surface roughness and formation of metal hydroxides. Herein, we attempt to use a chelating agent (EDTA) to reduce the surface roughness, improve the stability of cleaning solutions, and prevent the re-adsorption of impurities. The bonding between the cleaning solution and metal powder is analyzed by referring to the Pourbaix diagram. The changes in the ionic conductivity, H2O2 decomposition behavior, and degree of dissolution are checked with a conductivity meter, and the changes in the absorbance and particle size before and after the reaction are confirmed by ultraviolet-visible spectroscopy (UV-vis) and dynamic light scattering (DLS) analyses. Thus, the addition of a chelating agent prevents the decomposition of H2O2 and improves the life of the silicon wafer cleaning solution, allowing it to react smoothly with metallic impurities.