• Journal of the Korean Ceramic Society
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• v.28 no.6
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• pp.495-501
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• 1991

This study is intended to make defect-free region, denuded zone at the silicon wafer surface for semiconductor device substrates. In this experiment, initial oxygen concentration of starting material CZ-grown silicon wafer, various heat treatment combinations, denuding ambient and the amounts of oxygen reduction were measured, and then denuded zone (DZ) formation and depth were investigated. In Low/High anneal (DZ formation could be achieved), the optimum temperature for Low anneal was 700$^{\circ}C$∼750$^{\circ}C$. In case of High anneal, with the time increased, DZ depth was increased at 1000$^{\circ}C$, 1150$^{\circ}C$ respectively, but on the contrary, DZ depth was decreased at low temperature 900$^{\circ}C$. As well, out-diffusion time below 2 hours was unsuitable for effective Gettering technique even though the temperature was high, and DZ formation could be achieved when initial oxygen concentration was only above 14 ppm in silicon wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.13-16
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• 2000

Progress in Si crystal and wafer technologies is discussed on single crystal growth, wafer fabrication, epitaxial growth, gettering, 300 mm and SOI. As for bulk crystal growth, the mechanism of grown-in defects (voids) formation, the succes of grown-in defect free crystal growth technology and nitrogen doped crystal are shown. New wafer fabrication technologies such as both-side mirror polishing and etchingless process have been developed. The epitaxial growth of SiGe/Si heterostructure for high speed bipolar device is treated. Gettering technology under low temperature process such as RTP is important, and also it is shown that IG effect for Ni could be predicted using computer simulation of precipitate density and size. The development of 300 mm wafer and SOI has made progress steadily.

• Proceedings of the Korean Magnestics Society Conference
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• 2004.12a
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• pp.31-32
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• 2004

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.68-73
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• 2006

We propose a damascene gate FinFET with Si nanocrystals implemented on bulk silicon wafer for low voltage flash memory device. The use of optimized SRON (Silicon-Rich Oxynitride) process allows a high degree of control of the Si excess in the oxide. The FinFET with Si nanocrystals shows high program/erase (P/E) speed, large $V_{TH}$ shifts over 2.5V at 12V/$10{\mu}s$ for program and -12V/1ms for erase, good retention time, and acceptable endurance characteristics. Si nanocrystal memory with damascene gate FinFET is a solution of gate stack and voltage scaling for future generations of flash memory device. Index Terms-FinFET, Si-nanocrystal, SRON(Si-Rich Oxynitride), flash memory device.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.9 no.1
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• pp.38-44
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• 2000

The background of this study lies in he investigation of the formation mechanism of ductile mode(nkanometer-size) chips of brittle materials such as fine ceramics glass and silicon. As the first step to achieve this purpose this paper intends to observe the micro-deformation behavior of these materials in sub${\mu}{\textrm}{m}$ depth indentation tests using a diamond indentor. In this study it was developed Ultra-Micro Indentation. Device using the PZT actuator. Experimentally by using the Ultra-Micro Indentation device the micro fracture behavior of the silicon wafer was investigated. It was possible that ductile-brittle transition point in ultimate surface of brittle material can be detected by adding an acoustic emission sensor system to the Ultra-Micro Indentation appartus.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• IE interfaces
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• v.17 no.1
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• pp.1-12
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• 2004

In a modern semiconductor device manufacturing industry, statistical bin limits on wafer level test bin data are used for minimizing value added to defective product as well as protecting end customers from potential quality and reliability excursion. Most wafer level test bin data show skewed distributions. By Monte Carlo simulation, this paper evaluates methods and sample size effect regarding determination of statistical bin limits. In the simulation, it is assumed that wafer level test bin data follow the Poisson distribution. Hence, typical shapes of the data distribution can be specified in terms of the distribution's parameter. This study examines three different methods; 1) percentile based methodology; 2) data transformation; and 3) Poisson model fitting. The mean square error is adopted as a performance measure for each simulation scenario. Then, a case study is presented. Results show that the percentile and transformation based methods give more stable statistical bin limits associated with the real dataset. However, with highly skewed distributions, the transformation based method should be used with caution in determining statistical bin limits. When the data are well fitted to a certain probability distribution, the model fitting approach can be used in the determination. As for the sample size effect, the mean square error seems to reduce exponentially according to the sample size.

• Journal of Sensor Science and Technology
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• v.27 no.5
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• pp.300-305
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• 2018

The uncooled microbolometer thermal sensor for low cost and mass volume was designed to target the new infrared market that includes smart device, automotive, energy management, and so on. The microbolometer sensor features 80x60 pixels low-resolution format and enables the use of wafer-level vacuum packaging (WLVP) technology. Read-out IC (ROIC) implements infrared signal detection and offset correction for fixed pattern noise (FPN) using an internal digital to analog convertor (DAC) value control function. A reliable WLVP thermal sensor was obtained with the design of lid wafer, the formation of Au80%wtSn20% eutectic solder, outgassing control and wafer to wafer bonding condition. The measurement of thermal conductance enables us to inspect the internal atmosphere condition of WLVP microbolometer sensor. The difference between the measurement value and design one is $3.6{\times}10-9$ [W/K] which indicates that thermal loss is mainly on account of floating legs. The mean time to failure (MTTF) of a WLVP thermal sensor is estimated to be about 10.2 years with a confidence level of 95 %. Reliability tests such as high temperature/low temperature, bump, vibration, etc. were also conducted. Devices were found to work properly after accelerated stress tests. A thermal camera with visible camera was developed. The thermal camera is available for non-contact temperature measurement providing an image that merged the thermal image and the visible image.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.2
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• pp.1-6
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• 2008

In recent years, developments in the semiconductor and electronic industries have brought a rapid increase in the use of large size silicon wafer. For further improvement of the ultra precision surface and flatness of Si wafer necessary to high density ULSI, it is known that polishing is very important. However, most of these investigation was experiment less than 300mm diameter. Polishing is one of the important methods in manufacturing of Si wafers and in thinning of completed device wafers. This study reports the machining variables that has major influence on the characteristic of wafer polishing. It was adapted to polishing pressure, machining speed, and the slurry mix ratio, the optimum condition is selected by ultra precision wafer polishing using load cell and infrared temperature sensor. The optimum machining condition is selected a result data that use a pressure and table speed data. By using optimum condition, it achieves a ultra precision mirror like surface.