• Title/Summary/Keyword: Device Wafer

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Characterization of Light Effect on Photovoltaic Property of Poly-Si Solar Cell by Using Photoconductive Atomic Force Microscopy (Photoconductive Atomic Force Microscopy를 이용한 빛의 세기 및 파장의 변화에 따른 폴리실리콘 태양전지의 광전특성 분석)

  • Heo, Jinhee
    • Korean Journal of Materials Research
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    • v.28 no.11
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    • pp.680-684
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    • 2018
  • We investigate the effect of light intensity and wavelength of a solar cell device using photoconductive atomic force microscopy(PC-AFM). A $POCl_3$ diffusion doping process is used to produce a p-n junction solar cell device based on a polySi wafer, and the electrical properties of prepared solar cells are measured using a solar cell simulator system. The measured open circuit voltage($V_{oc}$) is 0.59 V and the short circuit current($I_{sc}$) is 48.5 mA. Moreover, the values of the fill factors and efficiencies of the devices are 0.7 and approximately 13.6 %, respectively. In addition, PC-AFM, a recent notable method for nano-scale characterization of photovoltaic elements, is used for direct measurements of photoelectric characteristics in limited areas instead of large areas. The effects of changes in the intensity and wavelength of light shining on the element on the photoelectric characteristics are observed. Results obtained through PC-AFM are compared with the electric/optical characteristics data obtained through a solar simulator. The voltage($V_{PC-AFM}$) at which the current is 0 A in the I-V characteristic curves increases sharply up to $18W/m^2$, peaking and slowly falling as light intensity increases. Here, $V_{PC-AFM}$ at $18W/m^2$ is 0.29 V, which corresponds to 59 % of the average $V_{oc}$ value, as measured with the solar simulator. Furthermore, while the light wavelength increases from 300 nm to 1,100 nm, the external quantum efficiency(EQE) and results from PC-AFM show similar trends at the macro scale but reveal different results in several sections, indicating the need for detailed analysis and improvement in the future.

A Study on CMP Pad Thickness Profile Measuring Device and Method (CMP 패드 두께 프로파일 측정 장치 및 방법에 관한 연구)

  • Lee, Tae-kyung;Kim, Do-Yeon;Kang, Pil-sik
    • Journal of the Korean Society of Industry Convergence
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    • v.23 no.6_2
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    • pp.1051-1058
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    • 2020
  • The chemical mechanical planarization (CMP) is a process of physically and chemically polishing the semiconductor substrate. The planarization quality of a substrate can be evaluated by the within wafer non-uniformity (WIWNU). In order to improve WIWNU, it is important to manage the pad profile. In this study, a device capable of non-contact measurement of the pad thickness profile was developed. From the measured pad profile, the profile of the pad surface and the groove was extracted using the envelope function, and the pad thickness profile was derived using the difference between each profile. Thickness profiles of various CMP pads were measured using the developed PMS and envelope function. In the case of IC series pads, regardless of the pad wear amount, the envelopes closely follow the pad surface and grooves, making it easy to calculate the pad thickness profile. In the case of the H80 series pad, the pad thickness profile was easy to derive because the pad with a small wear amount did not reveal deep pores on the pad surface. However, the pad with a large wear amount make errors in the lower envelope profile, because there are pores deeper than the grooves. By removing these deep pores through filtering, the pad flatness could be clearly confirmed. Through the developed PMS and the pad thickness profile calculation method using the envelope function, the pad life, the amount of wear and the pad flatness can be easily derived and used for various pad analysis.

The Design and Implementation of an Educational Computer Model for Semiconductor Manufacturing Courses (반도체 공정 교육을 위한 교육용 컴퓨터 모델 설계 및 구현)

  • Han, Young-Shin;Jeon, Dong-Hoon
    • Journal of the Korea Society for Simulation
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    • v.18 no.4
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    • pp.219-225
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    • 2009
  • The primary purpose of this study is to build computer models referring overall flow of complex and various semiconductor wafer manufacturing process and to implement a educational model which operates with a presentation tool showing device design. It is important that Korean semiconductor industries secure high competitive power on efficient manufacturing management and to develop technology continuously. Models representing the FAB processes and the functions of each process are developed for Seoul National University Semiconductor Research Center. However, it is expected that the models are effective as visually educational tools in Korean semiconductor industries. In addition, it is anticipated that these models are useful for semiconductor process courses in academia. Scalability and flexibility allow semiconductor manufacturers to customize the models and perform simulation education. Subsequently, manufacturers save budget.

A Study on the Breakdown in MHEMTs with InAlAs/InGaAs Heterostructure Grown on the GaAs substrate (InAlAs/InGaAs/GaAs MHEMT 소자의 항복 특성에 관한 연구)

  • Son, Myung-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.11
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    • pp.1-8
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    • 2011
  • One of the most important parameters that limit maximum output power of transistor is breakdown. InAlAs/InGaAs/GaAs Metamorphic HEMTs (MHEMTs) have some advantages, especially for cost, compared with InP-based ones. However, GaAs-based MHEMTs and InP-based HEMTs are limited by lower breakdown voltage for output power even though they have good microwave and millimeter-wave frequency performance with lower minimum noise figure. In this paper, InAlAs/$In_xGa_{1-x}As$/GaAs MHEMTs are simulated and analyzed for breakdown. The parameters affecting breakdown are investigated in the fabricated 0.1-${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ heterostructure on the GaAs wafer using the hydrodynamic transport model of a 2D commercial device simulator. The impact ionization and gate field effect in the fabricated device including deep-level traps are analyzed for breakdown. In addition, Indium mole-fraction-dependent impact ionization rates are proposed empirically for $In_{0.52}Al_{0.48}As/In_xGa_{1-x}As$/GaAs MHEMTs.

Dependance of Ionic Polarity in Semiconductor Junction Interface (반도체 접합계면이 가스이온화에 따라 극성이 달라지는 원인)

  • Oh, Teresa
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.19 no.6
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    • pp.709-714
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    • 2018
  • This study researched the reasons for changing polarity in accordance with junction properties in an interface of semiconductors. The contact properties of semiconductors are related to the effect of the semiconductor's device. Therefore, it is an important factor for understanding the junction characteristics in the semiconductor to increase the efficiency of devices. For generation of various junction properties, carbon-doped silicon oxide (SiOC) was deposited with various argon (Ar) gas flow rates, and the characteristics of the SiOC was varied based on the polarity in accordance with the Ar gas flows. Tin-doped zinc oxide (ZTO) as the conductor was deposited on the SiOC as an insulator to research the conductivity. The properties of the SiOC were determined from the formation of a depletion layer by the ionization reaction with various Ar gas flow rates due to the plasma energy. Schottky contact was good in the condition of the depletion layer, with a high potential barrier between the silicon (Si) wafer and the SiOC. The rate of ionization reactions increased when increasing the Ar gas flow rate, and then the potential barrier of the depletion layer was also increased owing to deficient ions from electron-hole recombination at the junction. The dielectric properties of the depletion layer changed to the properties of an insulator, which is favorable for Schottky contact. When the ZTO was deposited on the SiOC with Schottky contact, the stability of the ZTO was improved by the ionic recombination at the interface between the SiOC and the ZTO. The conductivity of ZTO/SiOC was also increased on SiOC film with ideal Schottky contact, in spite of the decreasing charge carriers. It increases the demand on the Schottky contact to improve the thin semiconductor device, and this study confirmed a high-performance device owing to Schottky contact in a low current system. Finally, the amount of current increased in the device owing to ideal Schottky contact.

Microdevice for Separation of Circulating Tumor Cells Using Embedded Magnetophoresis with V-shaped Ni-Co Nanowires and Immuno-nanomagnetic Beads

  • Park, Jeong Won;Lee, Nae-Rym;Cho, Sung Mok;Jung, Moon Youn;Ihm, Chunhwa;Lee, Dae-Sik
    • ETRI Journal
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    • v.37 no.2
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    • pp.233-240
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    • 2015
  • The novelty of this study resides in a 6"-wafer-level microfabrication protocol for a microdevice with a fluidic control system for the separation of circulating tumor cells (CTCs) from human whole blood cells. The microdevice utilizes a lateral magnetophoresis method based on immunomagnetic nanobeads with anti-epithelial cell adhesive molecule antibodies that selectively bind to epithelial cancer cells. The device consists of a top polydimethylsiloxane substrate for microfluidic control and a bottom substrate for lateral magnetophoretic force generation with embedded v-shaped soft magnetic microwires. The microdevice can isolate about 93% of the spiked cancer cells (MCF-7, a breast cancer cell line) at a flow rate of 40/100 mL/min with respect to a whole human blood/buffer solution. For all isolation, it takes only 10 min to process 400 mL of whole human blood. The fabrication method is sufficiently simple and easy, allowing the microdevice to be a mass-producible clinical tool for cancer diagnosis, prognosis, and personalized medicine.

Dry oxidation of Germanium through a capping layer

  • Jeong, Mun-Hwa;Kim, Dong-Jun;Yeo, In-Hwan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.143.1-143.1
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    • 2016
  • Ge is a promising candidate to replace Si in MOSFET because of its superior carrier mobility, particular that of the hole. However Ge oxide is thermodynamically unstable. At elevated temperature, GeO is formed at the interface of Ge and GeO2, and its formation increases the interface defect density, degrading its device performance. In search for a method to surmount the problem, we investigated Ge oxidation through an inert capped oxide layer. For this work, we prepared low doped n-type Ge(100) wafer by removing native oxide and depositing a capping layer, and show that GeO2 interface can be successfully grown through the capping layer by thermal oxidation in a furnace. The thickness and quality of thus grown GeO2 interface was examined by ellipsometry, XPS, and AFM, along with I-V and C-V measurements performed at 100K to 300K. We will present the result of our investigation, and provide the discussion on the oxide growth rate, interface state density and electrical characteristics in comparison with other studies using the direct oxidation method.

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The Study of WET Cleaning Effect on Deep Trench Structure for Trench MOSFET Technology (Trench MOSFET Technology의 Deep Trench 구조에서 WET Cleaning 영향에 대한 연구)

  • Kim, Sang-Yong;Jeong, Woo-Yang;Yi, Keun-Man;Kim, Chang-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.06a
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    • pp.88-89
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    • 2009
  • In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

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2MHz, 2kW RF Generator (2MHz, 2kW RF 전원장치)

  • Lee J.H.;Choi D.K.;Choi S.D.;Choi H.Y.;Won C,Y.;Kim S.S
    • Proceedings of the KIPE Conference
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    • 2003.07a
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    • pp.260-263
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    • 2003
  • When ICP(Inductive Coupled Plasma type etching and wafer manufacturing is being processed in semiconductor process, a noxious gas in PFC and CFC system is generated. Gas cleaning dry scrubber is to remove this noxious gas. This paper describes a power source device, 2MHz switching frequency class 2kW RF Generator, used as a main power source of the gas cleaning dry scrubber. The power stage of DC/DC converter is consist of full bridge type converter with 100kHz switching frequency Power amplifier is push pull type inverter with 2MHz switching frequency, and transmission line transformer. The adequacy of the circuit type and the reliability of generating plasma in various load conditions are verified through 50$\Omega$ dummy load and chamber experiments result.

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Study on Through Paths Inside the Air Pressure Pick-Up Head for Non-Contact Gripper (비접촉식 그리퍼 적용을 위한 공기압 파지식 헤드 내부 관통로 고찰)

  • Kim, Joon-Hyun
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.21 no.4
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    • pp.563-569
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    • 2012
  • In the semiconductor and display device production processes, the handling of sensitive objects needs new carrying technology. Floating carrying motion is a practical alternative solution for non-contact handling of parts and substrates. This paper presents a study of through paths inside the air pressure pick-up head to generate the floating motion. The air motion by conceptual designed paths inside the head gradually develops positive pressure and vacuum between narrow objects. Positive pressure occurs through the head tip before discharging outside of the head. Negative pressure is developed by evacuating the inside head bottom as result of the radial flow connecting the vertical through-holes. The numerical analysis was done to figure out the stable levitation caused by the two acting forces between surfaces. In comparing with the standard case that the levitation gap gets 0.7-0.9 mm, it confirms the suggested head characteristics to show floating capacity in accordance with the head size, number of through-hole, and locations of through-hole in succession of conceptual design for a prototype.