• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.2
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• pp.74-79
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• 2002

In the a rapid changes of the semiconductor manufacturing technologies for early 21st century, it may be safely said that a kernel of terms is the size increase of Si wafer and the size decrease of semiconductor devices. As the size of Si wafers increases and semiconductor device is miniaturized, the units of cleaning processes increases. A present cleaning technology is based upon RCA cleaning which consumes vast chemicals and ultra pure water (UPW) and is the high temperature process. Therefore, this technology gives rise to the environmental issue. To resolve this matter, candidates of advanced cleaning processes has been studied. One of them is to apply the electrolyzed water. In this work, Compared with surface on Si wafer with electrolyzed water cleaning and various chemicals cleaning, and analyzed Si wafer surface condition treated with elecoolyzed water by cleaning temperature and cleaning time. Especially. concentrate upon the contact angle. finally, contact angle on surface treated with cathode water cleaning is 17.28, and anode water cleaning is 34.1.

• Composites Research
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• v.20 no.5
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• pp.49-55
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• 2007

Nanocomposite blade for dicing semiconductor wafer is investigated for micro/nano-device and micro/nano-fabrication. While metal blade has been used for dicing of silicon wafer, polymer composite blades are used for machining of quartz wafer in semiconductor and cellular phone industry in these days. Organic-inorganic material selection is important to provide the blade with machinability, electrical conductivity, strength, ductility and wear resistance. Maintaining constant thickness with micro-dimension during shaping is one of the important technologies fer machining micro/nano fabrication. In this study the fabrication of blade by wet processing of mixing conducting nano ceramic powder, abrasive powder phenol resin and polyimide has been investigated using an experimental approach in which the thickness differential as the primary design criterion. The effect of drying conduction and post pressure are investigated. As a result wet processing techniques reveal that reliable results are achievable with improved dimension tolerance.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.112-112
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• 2012

Graphene has been considered as one of the potential post Si-materials due to its high mobility. [1] However, since graphene is semi-conductor with zero band gap, it is difficult to achieve high Ion/Ioff ratio, one of the most important requirements for commercial devices. There have been many attempts to open its band gap for high Ion/Ioff ratio, but most of them end up lowering the mobility. [2-5] Thus, we proposed and demonstrated a new device structure for graphene transistor based on one of the unique properties of graphene for high Ion/Ioff: using this approach, we were able to achieve the ratio over $10^5$. [6] Our device has several major advantages over previously proposed graphene based electronic devices. Since our device does not alter the given properties of graphene, such as opening the band gap, it has no fundamental issues on mobility degradations. In addition, our device is fully compatible with current Si technology and we were able to fabricate the devices with 6 inch wafer scale with CVD (Chemical Vapor Deposition) grown graphene. In this presentation, we will discuss about the details of our graphene device including the device structure and the detailed understanding of working mechanism. We will present device characteristics including I-V curves with $10^5$ on/off ratio. We will also present the performance of an inverter based on our devices. Finally, we will discuss the current issues and their potential solutions.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.751-754
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• 2003

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with pseudomorphic HEMTs. We have studied the calibration on the DC and RF characteristics of the MHEMT device using I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A1$_{0.48}$As modulation-doped heterostructure on the GaAs wafer. For the optimized device performance simulation, we calibrated the device performance of 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate MHEMT fabricated in our research center using the 2D ISE-DESSIS device simulator. With this calibrated parameter set, we have obtained very good reproducibility. The device simulation on the DC and RF characteristics exhibits good reproducibility for our 0.1-${\mu}{\textrm}{m}$ -gate MHEMT device compared with the measurements. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.ormance.

• Journal of the Semiconductor & Display Technology
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• v.10 no.1
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• pp.63-73
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• 2011

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with conventional pseudomorphic HEMTs (PHEMTs). For the optimized device design and development, we have performed the calibration on the DC characteristics of our fabricated 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure on the GaAs wafer using the hydrodynamic transport model of a commercial 2D ISE-DESSIS device simulator. The well-calibrated device simulation shows very good agreement with the DC characteristic of the 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.

• Journal of the Korean Vacuum Society
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• v.10 no.3
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• pp.361-367
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• 2001

Recently, Chemical Mechanical Polishing(CMP) has become a leading planarization technique as a method for silicon wafer planarization that can meet the more stringent lithographic requirement of planarity for the future submicron device manufacturing. The SOI(Silicon On Insulator) wafer has received considerable attention as bulk-alternative wafer to improve the performance of semiconductor devices. In this paper, the objective of study is to investigate Material Removal Rate(MRR) and surface micro-roughness effects of slurry and pad in the CMP process. When particle size of slurry is increased, Material Removal rate increase. Surface micro-roughness is greater influenced by pad than by particle size of slurry. As a result of AM measurement, surface micro-roughness was improved from 27 $\AA$ Rms to 0.64 $\AA$Rms.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.4
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• pp.12-18
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• 2002

Silicon on insulator(SOI) wafer is used in a variety of microsensor applications in which thermal deformations and other mechanical effects may dominate device Performance. One of major Problems associated with the manufacturing Processes of the microaccelerometer based on the tunneling current concept is thermal deformations and thermal stresses. This paper deals with finite element analysis(FEA) of residual thermal deformations causing popping up, which are induced in micrormaching processes of a microaccelerometer. The reason for this Popping up phenomenon in manufacturing processes of microaccelerometer may be the bending of the whole wafer or it may come from the way the underetching occurs. We want to seek after the real cause of this popping up phenomenon and diminish this by changing manufacturing processes of mic개accelerometer. In microaccelerometer manufacturing process, this paper intend to find thermal deformation change of the temperature distribution by tunnel gap and additional beams. The thermal behaviors analysis intend to use ANSYS V5.5.3.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.3
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• pp.15-19
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• 2003

In This paper, we developed 1.96 GHz air gap type FBAR BPF using ZnO as piezoelectric sputtered by RF magnetron at room temperature. FBAR BPF was fabricated by sputtering bottom electrode (Al), ZnO as piezoelectric and top electrode (Mo) on Si wafer one by one with RF magnetron sputter, then Si was dry etched to make an air hole. XRD test result of fabricated FBAR BPF showed that ZnO crystal was well pre-oriented as (002) and sigma value of XRC was 1.018. IL(Insertion loss) showed excellent result as 1 dB.

• Transactions of the Society of Information Storage Systems
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• v.2 no.3
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• pp.163-168
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• 2006

Small form factor optical pickup (SFFOP) corresponding to BD specifications is strongly proposed for the next-generation portable storage device. In order to generate SFFOP, small sized optical pickup has been fabricated. We have developed a small sited optical pickup that is called the integrated optical pickup (IOP). The fabrication method of this system is mainly dependant on the use of the wafer based micro fabrication technology, which has been used in MEMS process such as photolithography, reactive ion etching, wafer bonding, and packaging process. This approach has the merits for mass production and high assembling accuracy. In this study, to generate the small sized optical pickup for high recording capacity, IOP corresponding to BD specifications has been designed and developed, including three main parts, 1) design, fabrication and evaluation of objective lens unit, 2) design and fabrication of IOP and 3) evaluation process of FES and TES.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.51-56
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• 2004

We propose and fabricate an 1${\times}$2 asymmetric optical switch by TOE using SOI wafer based on silicon which has very large TOE figure and it is a good material for optical devices. SOI wafer consists of 3 layers; upper Si layer for device(waveguide;core, n=3.5), buried oxide layer for insulator(clad, n=1.5) and Si substrate layer. We designed 1${\times}$2 asymmetric y-branched single mode optical waveguide switch by BPM simulation and metal heater by heat transfer simulation. Fabricated switch shows about 3.5 watts of power consumption and over 20dB of crosstalk between output channels.