• 제목/요약/키워드: Device Simulator

검색결과 551건 처리시간 0.027초

고속열차 주행 안전성 시험을 위해 시뮬레이터로 구현한 대차 불안정 센서 (Bogie instability sensor using simulator for movement safety of the high speed train)

  • 최권희;김국진;이병원;이종우
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2007년도 춘계학술대회 논문집
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    • pp.1403-1407
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    • 2007
  • The bogie of Rolling Stock is the basic rolling component. It operates the train body, guides the body considering various tracks and offers comfort to passengers. We can verify the safety level of bogie about all factors through the first -grade scenario of Preliminary Hazard Analysis, but especially the horizontal acceleration sensor, equipped in each power bogie and trailer bogie, is the device, which makes it possible to test bogie instability and uncomfortable body movements by the method, similar to actual train driving, and in this context the necessity of this device becomes important. This paper would classify the main functions of driving sub system and examine the reliability, availability, maintainability and safety, which are main factors of RAMS. Especially, we would realize the bogie instability sensor with a simulator and offer the content in analyzing the data by the statistical method, which are obtained through the connected test with OBCS.

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다축 시뮬레이터의 변위-하중 보정에 관한 연구 (A study on Displacement-Load Calibration of Multi-Axis Simulator)

  • 정상화;류신호;신현성;김상석;박용래
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2000년도 춘계학술대회 논문집
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    • pp.591-594
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    • 2000
  • In the recent day, fatigue life prediction techniques play a major role in the design of components in the ground vehicle industry. Full scale durability testing in the laboratory is an essential of any fatigue life evaluation of components or structure of the automotive vehicle. Component testing is particulary important in today's highly competitive industries where the design to reduce weight and production costs must be balanced with the necessity to avoid expensive service failure. Generally, 3-axis durability testing device is used to carry out the fatigue test. In this paper, The operation software for simultaneously driving 3-axis vibration testing device is developed and the displacement of the 3-axis actuator is separately calibrated by LDT Moreover, the input and output data are displayed in windows of PC controller with real time.

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Epi층의 농도 및 두께 변화에 따른 Multi-RESURF SOI LDMOSFET의 특성분석 (Breakdown and On-state characteristics of the Multi-RESURF SOI LDMOSFET)

  • 김형우;김상철;서길수;김남균;김은동
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 하계학술대회 논문집 C
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    • pp.1578-1580
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    • 2002
  • The breakdown and on-state characteristics of the multi-RESURF SOI LDMOSFET is presented. P-/n-epi layer thickness and doping concentration is varied from $2{\mu}m{\sim}5{\mu}m$ and $1{\times}10^{15}/cm^3{\sim}9{\times}10^{15}/cm^3$ to obtain optimum breakdown voltage and on-resistance. The breakdown and on-state characteristics of the device is verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

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전류 제한 능력을 갖는 전력용 MOSFET의 Mixed-Mode 시뮬레이션 (Mixed-Mode Simulation of the Power MOSFET with Current Limiting Capability)

  • 윤종만;최연익;한민규
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 하계학술대회 논문집 C
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    • pp.1451-1453
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    • 1994
  • A monolithic current limiting power MOSFET, which may be easily fabricated by the conventional DMOS process, is proposed. The proposed current limiting MOSFET consists of main power cells, sensing cells, and NPN lateral bipolar transistor so that users can adjust the current limiting levels with only one external resistor. The behaviors of the proposed device are numerically simulated and analyzed by 2-D device simulator MEDICI and mixed-mode simulator CA-AAM(Circuit Analysis Advanced Application Module).

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OFF 전류의 감소를 위한 다결정 실리콘 박막 트랜지스터의 구조 연구 (A Study on the Structure of Polycrystalline Silicon Thin Film Transistor for Reducing Off-Current)

  • 오정민;민병혁;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 하계학술대회 논문집 B
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    • pp.1292-1294
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    • 1993
  • This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

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다층 리지스트 다층 기판 구조에서의 전자빔 리소그래피 공정을 위한 몬테카를로 시뮬레이터의 개발 (Development of a Monte Carlo Simulator for Electron Beam Lithography in Multi-Layer Resists and Multi-Layer Substrates)

  • 손명식;이진구;황호정
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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    • pp.53-56
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    • 2002
  • We have developed a Monte Carlo (MC) simulator for electron beam lithography in multi-layer resists and multi-layer substrates in order to fabricate and develop high-speed PHEMT devices for millimeter- wave applications. For the deposited energy calculation to multi-layer resists by electron beam in MC simulation, we modeled newly for multi-layer resists and heterogeneous multi-layer substrates. Using this model, we simulated T-gate or r-gate fabrication process in PHEMT device and showed our results with SEM observations.

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디바이스 서버를 이용한 모션 베이스 특성에 따른 시각적 동기화 (Device Server Based Synchronization of a Simulator Reflecting Motion Base Characteristics)

  • 박형근;김종국;정의정;송재복;고희동
    • 한국감성과학회:학술대회논문집
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    • 한국감성과학회 2002년도 추계학술대회 논문집
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    • pp.47-52
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    • 2002
  • 가상공간에서 탑승자에게 운동감을 제공하기 위해서 수많은 형태의 모션 시뮬레이터가 개발되어 왔다. 하지만 이러한 형태의 시뮬레이터들은 그 고유한 형태에 의해 정해진 동역학과 워시아웃 알고리즘을 거쳐야만 정밀한 시뮬레이터가 될 수 있다. 본 논문은 기존의 좁은 시야공간에서의 시뮬레이터가 아닌 넓은 시야를 제시하고, 모션 베이스와 독립적으로 운영되는 영상 제시기를 이용하여 탑승자에게 운동감을 제공하는 분리형 시뮬레이터를 대상으로 하여 영상과 모션을 동기화시켜서 제시하는 방법에 대해 논의하고자 한다.

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Non-Quasi-Static RF Model for SOI FinFET and Its Verification

  • Kang, In-Man
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권2호
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    • pp.160-164
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    • 2010
  • The radio frequency (RF) model of SOI FinFETs with gate length of 40 nm is verified by using a 3-dimensional (3-D) device simulator. This paper shows the equivalent circuit model which can be used in the circuit analysis simulator. The RMS modeling error of Y-parameter was calculated to be only 0.3 %.