• Title/Summary/Keyword: Design Speed

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Design and Performance Evaluation of ACA-TCP to Improve Performance of Congestion Control in Broadband Networks (광대역 네트워크에서의 혼잡 제어 성능 개선을 위한 ACA-TCP 설계 및 성능 분석)

  • Na, Sang-Wan;Park, Tae-Joon;Lee, Jae-Yong;Kim, Byung-Chul
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.10 s.352
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    • pp.8-17
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    • 2006
  • Recently, the high-speed Internet users increase rapidly and broadband networks have been widely deployed. However, the current TCP congestion control algorithm was designed for relatively narrowband network environments, and thus its performance is inefficient for traffic transport in broadband networks. To remedy this problem, the TCP having an enhanced congestion control algorithm is required for broadband networks. In this paper, we propose an improved TCP congestion control that can sufficiently utilize the large available bandwidth in broadband networks. The proposed algorithm predicts the available bandwidth by using ACK information and RTT variation, and prevents large packet losses by adjusting congestion window size appropriately. Also, it can rapidly utilize the large available bandwidth by enhancing the legacy TCP algorithm in congestion avoidance phase. In order to evaluate the performance of the proposed algorithm, we use the ns-2 simulator. The simulation results show that the proposed algorithm improves not only the utilization of the available bandwidth but also RTT fairness and the fairness between contending TCP flows better than the HSTCP in high bandwidth delay product network environment.

Multi-Threaded Parallel H.264/AVC Decoder for Multi-Core Systems (멀티코어 시스템을 위한 멀티스레드 H.264/AVC 병렬 디코더)

  • Kim, Won-Jin;Cho, Keol;Chung, Ki-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.11
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    • pp.43-53
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    • 2010
  • Wide deployment of high resolution video services leads to active studies on high speed video processing. Especially, prevalent employment of multi-core systems accelerates researches on high resolution video processing based on parallelization of multimedia software. In this paper, we propose a novel parallel H.264/AVC decoding scheme on a multi-core platform. Parallel H.264/AVC decoding is challenging not only because parallelization may incur significant synchronization overhead but also because software may have complicated dependencies. To overcome such issues, we propose a novel approach called Multi-Threaded Parallelization(MTP). In MTP, to reduce synchronization overhead, a separate thread is allocated to each stage in the pipeline. In addition, an efficient memory reuse technique is used to reduce the memory requirement. To verify the effectiveness of the proposed approach, we parallelized FFmpeg H.264/AVC decoder with the proposed technique using OpenMP, and carried out experiments on an Intel Quad-Core platform. The proposed design performs better than FFmpeg H.264/AVC decoder before the parallelization by 53%. We also reduced the amount of memory usage by 65% and 81% for a high-definition(HD) and a full high-definition(FHD) video, respectively compared with that of popular existing method called 2Dwave.

Design of Asynchronous System Bus Wrappers based on a Hybrid Ternary Data Encoding Scheme (하이브리드 터너리 데이터 인코딩 기반의 비동기식 시스템 버스 래퍼 설계)

  • Lim, Young-Il;Lee, Je-Hoon;Lee, Seung-Sook;Cho, Kyoung-Rok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.1
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    • pp.36-44
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    • 2007
  • This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

Hybrid (refrctive/diffractive) lens design for the ultra-compact camera module (초소형 영상 전송 모듈용 DOE(Diffractive optical element)렌즈의 설계 및 평가)

  • Lee, Hwan-Seon;Rim, Cheon-Seog;Jo, jae-Heung;Chang, Soo;Lim, Hyun-Kyu
    • Korean Journal of Optics and Photonics
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    • v.12 no.3
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    • pp.240-249
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    • 2001
  • A high speed ultra-compact lens with a diffractive optical element (DOE) is designed, which can be applied to mobile communication devices such as IMT2000, PDA, notebook computer, etc. The designed hybrid lens has sufficiently high performance of less than f/2.2, compact size of 3.3 mm (1st surf. to image), and wide field angle of more than 30 deg. compared with the specifications of a single lens. By proper choice of the aspheric and DOE surface which has very large negative dispersion, we can correct chromatic and high order aberrations through the optimization technique. From Seidel third order aberration theory and Sweatt modeling, the initial data and surface configurations, that is, the combination condition of the DOE and the aspherical surface are obtained. However, due to the consideration of diffraction efficiency of a DOE, we can choose only four cases as the optimization input, and present the best solution after evaluating and comparing those four cases. On the other hand, we also report dramatic improvement in optical performance by inserting another refractive lens (so-called, field flattener), that keeps the refractive power of an original DOE lens and makes the petzval sum zero in the original DOE lens system. ystem.

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Division of Homogeneous Road Sections for National Highway by Genetic Algorithms (유전자 알고리즘을 적용한 국도의 동질성 구간 분할)

  • Oh, Ju-Sam;Lim, Sung-Han;Cho, Yoon-Ho
    • International Journal of Highway Engineering
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    • v.7 no.4 s.26
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    • pp.41-47
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    • 2005
  • Traffic data such as traffic volume, speed, and vehicle Class are very important basic data for the plan and design of highway. Based on traffic data, the future service level of a specific highway and geometry of newly constructed or expended road is predicted and determined. The Ministry of Construction & Transportation has simultaneously surveyed coverage count and permanent count at highways since 1985. Traffic volume survey sections were determined at jointed nodes of highways and jointed nodes of highways and other roads such as freeway and local highway. Volume survey was performed at these sections. The premise to decide these sections is assumed that links between jointed nodes of main highways exhibit similar traffic characteristics. Recently, due to the change of highway geometries such as construction of detour road and installations of traffic facilities such as installation of media, traffic characteristics of the existing traffic volume survey sections was changed. To reflect these changes, traffic characteristics at homogeneous road sections was widely evaluated and analyzed. Using Genetic Algorithms, a model was developed for the evaluation of traffic characteristics at homogeneous road sections. Traffic volume survey sections were then determined through the application of the developed model for current traffic system.

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Design and Performance Analysis of the Efficient Equalization Method for OFDM system using QAM in multipath fading channel (다중경로 페이딩 채널에서 QAM을 사용하는 OFDM시스템의 효율적인 등화기법 설계 및 성능분석)

  • 남성식;백인기;조성호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.6B
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    • pp.1082-1091
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    • 2000
  • In this paper, the efficient equalization method for OFDM(Orthogonal Frequency Division Multiflexing) System using the QAM(Quadrature Amplitude Modulation) in multipath fading channel is proposed in order to faster and more efficiently equalize the received signals that are sent over real channel. In generally, the one-tap linear equalizers have been used in the frequency-domain as the existing equalization method for OFDM system. In this technique, if characteristics of the channel are changed fast, the one-tap linear equalizers cannot compensate for the distortion due to time variant multipath channels. Therefore, in this paper, we use one-tap non-linear equalizers instead of using one-tap linear equalizers in the frequency-domain, and also use the linear equalizer in the time-domain to compensate the rapid performance reduction at the low SNR(Signal-to-Noise Ratio) that is the disadvantage of the non-linear equalizer. In the frequency-domain, when QAM signals, consisting of in-phase components and quadrature (out-phase) components, are sent over the complex channel, the only in-phase and quadrature components of signals distorted by the multipath fading are changed the same as signals distorted by the noise. So the cross components are canceled in the frequency-domain equalizer. The time-domain equalizer and the adaptive algorithm that has lower-error probability and fast convergence speed are applied to compensate for the error that is caused by canceling the cross components in the frequency-domain equalizer. In the time-domain, To compensate for the performance of frequency-domain equalizer the time-domain equalizes the distorted signals at a frame by using the Gold-code as a training sequence in the receiver after the Gold-codes are inserted into the guard signal in the transmitter. By using the proposed equalization method, we can achieve faster and more efficient equalization method that has the reduced computational complexity and improved performance.

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Development of Estimation Method for Velocity Pressure Exposure Coefficient of Buildings Based on Spatial Information (공간정보기반 건축물의 풍속고도분포계수 산정 방법 개발)

  • SEO, Eun-Su;CHOI, Se-Hyu
    • Journal of the Korean Association of Geographic Information Studies
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    • v.20 no.2
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    • pp.32-46
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    • 2017
  • Recent rapid urban expansion and crowding of various industrial facilities has affected the features of a significant part of downtown area, resulting in areas having buildings with a wide range of height and the foothills. To compute a velocity pressure exposure coefficient, namely the design wind speed factor, this study defines ground surface roughness by utilizing concentration analysis for the height of each building. After obtaining spatial data by extracting a building layer from digital maps, the study area was partitioned for the concentration analysis and to allow investigation of the frequency distribution of building heights. Concentration analysis by building height was determined with the Variation-to-Means Ratio (VMR) and Poisson distribution analysis using a buildings distribution chart, with statistical significance determined using Chi-square verification. Applying geographic information systems (GIS) with the architectural information made it possible to estimate a velocity pressure exposure coefficient factor more quantitatively and objectively, by including geographic features, as compared to current methods. Thus, this method is expected to eliminate inaccuracies that arise when building designers calculate the velocity pressure exposure coefficient in subjective way, and to help increase the wind resistance of buildings in a more logical and cost-effective way.

A 200-MHz@2.5V 0.25-$\mu\textrm{m}$ CMOS Pipelined Adaptive Decision-Feedback Equalizer (200-MHz@2.5-V 0.25-$\mu\textrm{m}$ CMOS 파이프라인 적응 결정귀환 등화기)

  • 안병규;이종남;신경욱
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.05a
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    • pp.465-469
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    • 2000
  • This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

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Real-Time Fixed Pattern Noise Suppression using Hardware Neural Networks in Infrared Images Based on DSP & FPGA (DSP & FPGA 기반의 적외선 영상에서 하드웨어 뉴럴 네트워크를 이용한 실시간 고정패턴잡음 제어)

  • Park, Chang-Han;Han, Jung-Soo;Chun, Seung-Woo
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.46 no.4
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    • pp.94-101
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    • 2009
  • In this paper, we propose design of hardware based on a high speed digital signal processor (DSP) and a field programmable gate array (FPGA) for real-time suppression of fixed pattern noise (FPN) using hardware neural networks (HNN) in cooled infrared focal plane array (IRFPA) imaging system FPN appears a limited operation by temperature in observable images which applies to non-uniformity correction for infrared detector. These have very important problems because it happen serious problem for other applications as well as degradation for image quality in our system Signal processing architecture for our system operates reference gain and offset values using three tables for low, normal, and high temperatures. Proposed method creates virtual tables to separate for overlapping region in three offset tables. We also choose an optimum tenn of temperature which controls weighted values of HNN using mean values of pixels in three regions. This operates gain and offset tables for low, normal, and high temperatures from mean values of pixels and it recursively don't have to do an offset compensation in operation of our system Based on experimental results, proposed method showed improved quality of image which suppressed FPN by change of temperature distribution from an observational image in real-time system.

A Design of DLL-based Low-Power CDR for 2nd-Generation AiPi+ Application (2세대 AiPi+ 용 DLL 기반 저전력 클록-데이터 복원 회로의 설계)

  • Park, Joon-Sung;Park, Hyung-Gu;Kim, Seong-Geun;Pu, Young-Gun;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.4
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    • pp.39-50
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    • 2011
  • In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.