• Title/Summary/Keyword: Design Circuit and Modeling

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Design and Fabrication of Multilayer Diplexer for Dual Band GSM/DCS Applications using Lumped Elements (집중 소자를 이용한 이중 대역 GSM/DCS용 적층형 다이플렉서의 설계 및 제작)

  • 심성훈;강종윤;최지원;윤영중;김현재;윤석진
    • Journal of the Korean Ceramic Society
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    • v.40 no.11
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    • pp.1090-1095
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    • 2003
  • In this paper, the modeling and design of high-Q multilayer passives and multilayer diplexer for GSM/DCS applications designed and fabricated using these passives have been investigated.. To miniaturize the system, configurations of inductor and capacitor have involved a square spiral structure and a vertically-interdigitated capacitor similar to 3D interdigital structure, respectively. Multilayer diplexers for GSM/DCS applications were designed and fabricated to apply high-Q multilayer passives to practical systems, which were designed by the proposed structural and equivalent circuit model. LPF for GSM band had the passband insertion loss of less than 0.55 dB, the return loss of more than 12 dB, and the isolation level of more than 26 dB by locating attenuation pole at 1800 MHz. HPF for DCS band had the passband insertion loss of less than 0.82 dB, the return loss of more than 11 dB, and the isolation level of more than 38 dB by locating attenuation pole at 930 MHz.

A Substrate Resistance and Guard-ring Modeling for Noise Analysis of Twin-well Non-epitaxial CMOS Substrate (Twin-well Non-epitaxial CMOS Substrate에서의 노이즈 분석을 위한 Substrate Resistance 및 Guard-ring 모델링)

  • Kim, Bong-Jin;Jung, Hae-Kang;Lee, Kyoung-Ho;Park, Hong-June
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.4
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    • pp.32-42
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    • 2007
  • The substrate resistance is modeled to estimate the performance degradation of analog circuits by substrate noise in a $0.35{\mu}m$ twin-well non-epitaxial CMOS process. The substrate resistance model equations are applied to the P+ guard-ring isolation structure and a good match was achieved between measurements and models. The substrate resistance is divided into four types and a semi-empirical model equation is obtained for each type of substrate resistance. The rms(root-mean-square) error of the substrate resistance model is below 10% compared with the measured resistance. To apply this substrate resistance model to the P+ guard ring structure, ADS(Advanced Design System) circuit simulation results are compared with the measurement results using Network Analyzer, and relatively good agreements are obtained between measurements and simulations.

A Study of Electromagnetic Coupling Analysis between Dipole Antenna and Transmission Line Using PEEC Method (PEEC 방법을 이용한 다이폴 안테나와 전송선로 사이의 전자기 결합 분석에 관한 연구)

  • Oh, Jeongjoon;Kim, Kwangho;Park, Myeongkoo;Lee, Hosang;Nah, Wansoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.28 no.11
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    • pp.902-915
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    • 2017
  • In recent years, mobile devices have become increasingly multi-functional and high performance, resulting in a dramatical increase in processing speed. On the other hand, the size of device is reduced, circuits inside the device are more easily exposed to electromagnetic interference radiated from antenna or adjacent circuits, degrading the system performance. To prevent this, it is necessary to design the device considering the electromagnetic characteristics with EM simulation at the design stage of product. However, the EM simulation takes a long analysis time and require high-level system resources for fast analysis. In this paper, an equivalent circuit modeling method for a round wire is proposed using a PEEC method and the electromagnetic coupling from a dipole antenna to a transmission line is analyzed in frequency domain. And compared with the result of electromagnetic simulator. As a result, PEEC method shows good agreement with those of electromagnetic simulation, in a much more short time.

Modeling and Simulation of the Cardiovascular System Using Baroreflex Control Model of the Heart Activity (심활성도 압반사 제어 모델을 이용한 심혈관시스템 모델링 및 시뮬레이션)

  • Choi Byeong Cheol;Jeong Do Un;Shon Jung Man;Yae Su Yung;Kim Ho Jong;Lee Hyun Cheol;Kim Yun Jin;Jung Dong keun;Yi Sang Hun;Jeon Gye Rok
    • Journal of Biomedical Engineering Research
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    • v.25 no.6
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    • pp.565-573
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    • 2004
  • In this paper, we proposed a heart activity control model for simulation of the aortic sinus baroreceptor, which was the most representative baroreceptor sensing the variance of pressure in the cardiovascular system. And then, the heart activity control model composed electric circuit model of the cardiovascular system with baroreflex control and time delay sub-model to observe the effect of time delay in heart period and stroke volume under the regulation of baroreflex in the aortic sinus. The mechanism of time delay in the heart activity baroreflex control model is as follows. A control function is conduct sensing pressure information in the aortic sinus baroreceptor to transmit the efferent nerve through central nervous system. As simulation results of the proposed model, we observed three patterns of the cardiovascular system variability by the time delay. First of all, if the time delay over 2.5 second, aortic pressure and stroke volume and heart rate was observed non-periodically and irregularly. However, if the time delay from 0.1 second to 0.25 second, the regular oscillation was observed. And then, if time delay under 0.1 second, then heart rate and aortic pressure-heart rate trajectory were maintained in stable state.

Multi-Secondary Transformer: A Modeling Technique for Simulation - II

  • Patel, A.;Singh, N.P.;Gupta, L.N.;Raval, B.;Oza, K.;Thakar, A.;Parmar, D.;Dhola, H.;Dave, R.;Gupta, V.;Gajjar, S.;Patel, P.J.;Baruah, U.K.
    • Journal of international Conference on Electrical Machines and Systems
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    • v.3 no.1
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    • pp.78-82
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    • 2014
  • Power Transformers with more than one secondary winding are not uncommon in industrial applications. But new classes of applications where very large number of independent secondaries are used are becoming popular in controlled converters for medium and high voltage applications. Cascade H-bridge medium voltage drives and Pulse Step Modulation (PSM) based high voltage power supplies are such applications. Regulated high voltage power supplies (Fig. 1) with 35-100 kV, 5-10 MW output range with very fast dynamics (${\mu}S$ order) uses such transformers. Such power supplies are widely used in fusion research. Here series connection of isolated voltage sources with conventional switching semiconductor devices is achieved by large number of separate transformers or by single unit of multi-secondary transformer. Naturally, a transformer having numbers of secondary windings (~40) on single core is the preferred solution due to space and cost considerations. For design and simulation analysis of such a power supply, the model of a multi-secondary transformer poses special problem to any circuit analysis software as many simulation softwares provide transformer models with limited number (3-6) of secondary windings. Multi-Secondary transformer models with 3 different schemes are available. A comparison of test results from a practical Multi-secondary transformer with a simulation model using magnetic component is found to describe the behavior closer to observed test results. Earlier models assumed magnetising inductance in a linear loss less core model although in actual it is saturable core made-up of CRGO steel laminations. This article discusses a more detailed representation of flux coupled magnetic model with saturable core properties to simulate actual transformers very close to its observed parameters in test and actual usage.

Design of a radiation-tolerant I-gate n-MOSFET structure and analysis of its characteristic (I 형 게이트 내방사선 n-MOSFET 구조 설계 및 특성분석)

  • Lee, Min-woong;Cho, Seong-ik;Lee, Nam-ho;Jeong, Sang-hun;Kim, Sung-mi
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.10
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    • pp.1927-1934
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    • 2016
  • In this paper, we proposed a I-gate n-MOSFET (n-type Metal Oxide Semiconductors Field Effect Transistor) structure in order to mitigate a radiation-induced leakage current path in an isolation oxide interface of a silicon-based standard n-MOSFET. The proposed I-gate n-MOSFET structure was designed by using a layout modification technology in the standard 0.18um CMOS (Complementary Metal Oxide Semiconductor) process, this structure supplements the structural drawbacks of conventional radiation-tolerant electronic device using layout modification technology such as an ELT (Enclosed Layout Transistor) and a DGA (Dummy Gate-Assisted) n-MOSFET. Thus, in comparison with the conventional structures, it can ensure expandability of a circuit design in a semiconductor-chip fabrication. Also for verification of a radiation-tolerant characteristic, we carried out M&S (Modeling and Simulation) using TCAD 3D (Technology Computer Aided Design 3-dimension) tool. As a results, we had confirmed the radiation-tolerant characteristic of the I-gate n-MOSFET structure.

Macroscopic High-Temperature Structural Analysis Model for a Small-Scale PCHE Prototype (I) (소형 PCHE 에 대한 거시적 고온 구조 해석 모델링 (I))

  • Song, Kee-Nam;Lee, Heong-Yeon;Kim, Chan-Soo;Hong, Sung-Duk;Park, Hong-Yoon
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.35 no.11
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    • pp.1499-1506
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    • 2011
  • The IHX (intermediate heat exchanger) is a key component of nuclear hydrogen systems for the production of massive amounts hydrogen. The IHX transfers the $950^{\circ}C$ heat generated by the VHTR (very high temperature reactor) to a hydrogen production plant. The Korea Atomic Energy Research Institute established a small-scale gas loop to test the performance of key VHTR components and manufactured a small-scale PCHE (printed circuit heat exchanger) prototype, which is being considered as a candidate for the IHX, for testing in the small-scale gas loop. In this study, as a part of the high-temperature structural integrity evaluation of the small-scale PCHE prototype, we carried out high-temperature structural analysis modeling and macroscopic thermal and structural analysis for the small-scale PCHE prototype under the small-scale gas loop test conditions. This analysis serves as a precedent study to scheduled PCHE performance test in the small-scale gas loop. The results obtained in this study will be compared with the test results for the small-scale PCHE and then used to design the medium-scale PCHE prototype.

A Study on Motion Estimator Design Using DCT DC Value (DCT 직류 값을 이용한 움직임 추정기 설계에 관한 연구)

  • Lee, Gwon-Cheol;Park, Jong-Jin;Jo, Won-Gyeong
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.3
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    • pp.258-268
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    • 2001
  • The compression method is necessarily used to send the high quality moving picture that contains a number of data in image processing. In the field of moving picture compression method, the motion estimation algorithm is used to reduce the temporal redundancy. Block matching algorithm to be usually used is distinguished partial search algorithm with full search algorithm. Full search algorithm be used in this paper is the method to compare the reference block with entire block in the search window. It is very efficient and has simple data flow and control circuit. But the bigger the search window, the larger hardware size, because large computational operation is needed. In this paper, we design the full search block matching motion estimator. Using the DCT DC values, we decide luminance. And we apply 3 bit compare-selector using bit plane to I(Intra coded) picture, not using 8 bit luminance signals. Also it is suggested that use the same selective bit for the P(Predicted coded) and B(Bidirectional coded) picture. We compare based full search method with PSNR(Peak Signal to Noise Ratio) for C language modeling. Its condition is the reference block 8$\times$8, the search window 24$\times$24 and 352$\times$288 gray scale standard video images. The result has small difference that we cannot see. And we design the suggested motion estimator that hardware size is proved to reduce 38.3% for structure I and 30.7% for structure II. The memory is proved to reduce 31.3% for structure I and II.

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IPv6 Migration, OSPFv3 Routing based on IPv6, and IPv4/IPv6 Dual-Stack Networks and IPv6 Network: Modeling, and Simulation (IPv6 이관, IPv6 기반의 OSPFv3 라우팅, IPv4/IPv6 듀얼 스택 네트워크와 IPv6 네트워크: 모델링, 시뮬레이션)

  • Kim, Jeong-Su
    • The KIPS Transactions:PartC
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    • v.18C no.5
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    • pp.343-360
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    • 2011
  • The objective of this paper is to analyze and characterize to simulate routing observations on end-to-end routing circuits and a ping experiment of a virtual network after modeling, such as IPv6 migration, an OSPFv3 routing experiment based on an IPv6 environment, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing using IPv6 planning and operations in an OPNET Modeler. IPv6 deployment based largely on the integrated wired and wireless network was one of the research tasks at hand. The previous studies' researchers recommended that future research work be done on the explicit features of both OSPFv3 and EIGRP protocols in the IPv4/IPv6 environment, and more research should be done to explore how to improve the end-to-end IPv6 performance. Also, most related work was performed with an IPv4 environment but lacked studies related to the OSPFv3 virtual network based on an end-to-end IPv6 environment. Hence, this research continues work in previous studies in analyzing IPv6 migration, an OSPFv3 routing experiment based on IPv6, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing. In the not too distant future, before enabling the default IPv6, it would help to understand network design and deployment based on an IPv6 environment through IPv6 planning and operations for the end-user perspective such as success or failure of connection on IPv6 migration, exploration of an OSPFv3 routing circuit based on an end-to-end IPv6 environment, and a ping experiment for IPv4/IPv6 dual-stack networks and IPv6 network for OSPFv3 routing. We were able to observe an optimal route for modeling of an end-to-end virtual network through simulation results as well as find what appeared to be a fast ping response time VC server to ensure Internet quality of service better than an HTTP server.

Convergence Comparison of Linear Oscillating Electric Machines (리니어 오실레이팅 전기기기의 비교 연구)

  • Jeong, Sung-In;Eom, Sang In
    • Journal of the Korea Convergence Society
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    • v.12 no.12
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    • pp.273-280
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    • 2021
  • This paper presents the results of study of linear oscillating electric machine; Cartesian, cylindrical type with permanent magnet, flux reversal, cylindrical reluctance, and transverse flux type. The focus of the work is the suggestion of the characteristics and design process of propose topology, respectively. First of all, there are five types of the proposed to this study on the basis of the existing literatures; Cartesian type, cylindrical type, flux reversal type, cylindrical reluctance type, and transverse flux type. All topology is achieved using equivalent magnetic circuit considering leakage elements as initial modeling. Cartesian type is investigated by number of phases and number of pole pairs using optimal process. A cylindrical type is described by number of phases and displacement of stroke. The flux reversal type is proposed based on the symmetrical and non symmetrical stator cores of the surface mounted PMs mover, and non slanted PMs and slanted PMs of the flux concentrating PMs mover. A cylindrical reluctance type is studied by the shape of mover teeth in geometric aspect to reduce force ripple and increase magnetic flux. A transverse flux type is considered by dividing the transverse flux electric excited and the transverse flux permanent magnet excited. It is significant that the study gives a design rules and features of linear oscillating electric machine.